Nonvolatile Memory Address Recovery for Faster Read Operations
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Solution Overview
Problem
The increasing size of data stored in storage devices and the need for improved operating speed in host devices necessitate enhanced error correction and data management to optimize read operations.
Innovation Solution
A storage device with a nonvolatile memory device and a controller that includes error correction and encryption modules to manage physical and logical addresses, utilizing a host performance booster (HPB) to accelerate data retrieval by pre-loading physical addresses in the host memory, and employing error correction and decryption processes to ensure efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction decoding is performed on physical address entries, then data retrieval accuracy is improved, but processing time increases
Solution Approach 1:
The patent performs error correction decoding on physical address entries in advance during the address translation process, before actual data retrieval operations. This preliminary error correction ensures that corrupted addresses are detected and corrected beforehand, preventing failed data retrieval attempts and reducing overall processing time despite the added decoding step.
Solution Approach 2:
The patent implements error correction code (ECC) protection on physical address entries stored in the host performance booster cache. By adding redundancy bits and performing error correction decoding, the system creates a protective cushion against bit errors that may occur during address storage or retrieval, ensuring reliable address translation even in the presence of errors.
2Speed
If physical addresses are pre-loaded in host memory using HPB, then data retrieval speed is improved, but memory usage increases
Solution Approach 1:
The patent implements the host performance booster cache with a specific capacity (e.g., 256 MB) dedicated to storing frequently accessed physical address entries. This localized high-speed storage area provides quick access to critical address information without requiring the entire system memory to be upgraded, balancing speed improvement with controlled memory consumption.
Solution Approach 2:
The patent creates a copy of frequently used physical address entries from the main storage system into the HPB cache memory. This copying mechanism allows the system to maintain a smaller, faster subset of address data that can be quickly accessed during address translation, reducing the need to access slower main storage for every address lookup.
3Reliability
If error correction encoding is performed on physical addresses, then data integrity is improved, but processing complexity increases
Solution Approach 1:
The patent extracts the error correction functionality into a dedicated ECC encoder module within the storage device controller. This separate module handles error correction encoding independently from the main address translation logic, simplifying the overall system architecture by isolating complexity into a specialized component that can be optimized separately.
Solution Approach 2:
The patent uses standardized error correction code parameters (such as BCH or LDPC code rates) that are commonly implemented in storage systems. By adopting established error correction schemes with known performance characteristics, the system achieves reliable error protection without requiring custom complex algorithms, reducing implementation complexity while maintaining high data integrity.
Data Source
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AI summary
There is provided a storage device which includes a nonvolatile memory device that includes a first area and a second area, and a controller that receives a first command from an external host device, generates a physical address by performing first error correction decoding on a physical address entry included in the first command, reads first data from the second area of the nonvolatile memory device by using the physical address, and outputs the first data to the external host device. When the first error correction decoding fails, the controller reads first map data from the first area from the nonvolatile memory device, translates a logical address included in the first command into the physical address by using the first map data, reads the first data from the second area of the nonvolatile memory device by using the physical address, and outputs the first data to the external host device.