Semiconductor Memory Device Address Registration Unit for Defective Block Management
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Solution Overview
Problem
Semiconductor memory devices face challenges in maximizing the number of valid blocks due to the inefficiencies in managing defective blocks across multiple physical planes, leading to reduced memory capacity and increased management load.
Innovation Solution
The semiconductor memory device employs a register system with address registration units that compare and convert physical block addresses between planes, allowing for the combination of normal and defective blocks to form valid logical blocks, thereby increasing the number of usable blocks without increasing the load on the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address replacement is performed using conventional methods with separate normal and redundant memory areas, then defective blocks can be managed, but the number of valid blocks is reduced and memory capacity is wasted
Solution Approach 1:
The patent merges the normal memory area and redundant memory area into a unified management system. By combining blocks from different physical planes and dynamically allocating them based on defect status, the system maximizes the number of valid logical blocks while maintaining reliable defective block management. The address registration unit integrates address management across multiple planes, eliminating the waste of dedicated redundant areas.
Solution Approach 2:
The patent implements dynamic address management where the address registration unit can flexibly allocate physical blocks to logical blocks based on real-time defect status. Instead of static allocation, the system dynamically determines which physical blocks to use, allowing optimal utilization of available memory resources while handling defects as they occur.
2Reliability
If conventional address replacement methods are used, then defective blocks can be replaced, but the management load on the memory controller increases
Solution Approach 1:
The patent implements self-service by embedding the address registration unit directly within the memory device. This unit automatically compares physical addresses, detects defective blocks, and performs address conversion without requiring external intervention from the memory controller. The memory device independently manages its own address allocation and defect handling, significantly reducing the management load on the controller.
Solution Approach 2:
The address registration unit acts as an intermediary between the physical memory blocks and the logical address space. It receives physical addresses, compares them against registered defective block addresses, and outputs converted addresses that map to valid physical blocks. This intermediary function simplifies the controller's task by handling the complex address conversion and defect management internally.
3Quantity of substance
If multiple physical planes are used to increase memory capacity, then storage capability is improved, but the complexity of managing defective blocks across planes increases
Solution Approach 1:
The address registration unit is designed with universal functionality to handle address management across multiple physical planes. It can register and compare addresses from any physical plane against a unified defective block address register, providing consistent defect management regardless of which plane is involved. This multi-functional approach simplifies cross-plane management while maintaining the benefits of increased memory capacity.
Data Source
AI summary
A semiconductor memory device having first and second physical planes each including a plurality of physical blocks of memory cells, includes a first register in which a first address is to be stored, a second register in which a second address associated with the first address is to be stored, a third register in which third addresses are to be stored, and an address registration unit including a first circuit configured to compare the first address stored in the first register with the third addresses and store the first address in the second register as the second address if the first address does not match any of the third addresses, and a second circuit configured to convert the first address into another address that is stored in the second register as the second address when the first address matches one of the third addresses.