Memory Address Mapping for Flexible Failed-Row Remapping
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Solution Overview
Problem
Current memory devices have limited memory replacement capabilities due to preset redundant spaces, leading to performance loss and inability to meet fault requirements, as users cannot customize or expand the replacement function.
Innovation Solution
A memory mapping method that allows flexible definition of address mapping table integration and redundant resource usage, enabling multiple reversible replacements through a user-customizable matching and searching circuit integrated into the memory access path, allowing for user-defined reserved space and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If preset redundant space is used for memory replacement, then memory replacement function is provided, but the quantity of times of memory replacement is limited and service performance loss occurs
Solution Approach 1:
The patent implements dynamic memory replacement by introducing an address mapping table that can be updated multiple times. The mapping table stores correspondence relationships between physical addresses and logical addresses, allowing the system to dynamically adjust replacement mappings as memory failures occur, rather than relying on fixed preset redundant space.
Solution Approach 2:
The patent introduces an address mapping table as an intermediary layer between the physical memory and the logical address space. This mapping table acts as a mediator that translates logical addresses to physical addresses, enabling flexible remapping of failed memory regions to healthy regions without requiring preset redundant space in the physical memory itself.
2Reliability
If redundant space is preset in memory device, then replacement function is available, but redundant space cannot be changed and fault requirement cannot be met
Solution Approach 1:
The system enables dynamic adjustment of reserved space configuration through software-based address mapping tables. The size and location of reserved spaces can be modified by updating the mapping table entries, allowing the system to adapt to different fault scenarios and requirements without physical reconfiguration of the memory device.
Solution Approach 2:
The patent changes the parameters of memory allocation by using address mapping tables that can be configured with different mapping relationships. This allows flexible adjustment of reserved space parameters (size, location, allocation) through software configuration rather than hardware constraints, enabling customization according to specific fault requirements.
3Reliability
If address mapping table is integrated into memory access path, then multiple reversible replacements can be implemented, but device complexity increases
Solution Approach 1:
The patent replaces complex hardware-based replacement mechanisms with a software-based address mapping table approach. Instead of using dedicated hardware circuits for each replacement scenario, the system uses programmable mapping tables that can be updated via software, significantly reducing hardware complexity while maintaining or improving reliability.
Solution Approach 2:
The address mapping table serves multiple functions: it handles address translation, manages memory replacement, tracks failed memory regions, and enables reversible replacements. This single universal data structure replaces what would otherwise require multiple specialized hardware components, reducing overall system complexity.
Data Source
AI summary
A memory mapping method includes: obtaining a memory failed row address of a first memory; obtaining, by a matching and searching circuit, an address mapping table, where the address mapping table includes a mapping relationship between the memory failed row address and a memory remapping row address corresponding to the memory failed row address; and when an access target of the first memory is the memory failed row address, obtaining, based on the address mapping table, the memory remapping row address to which the memory failed row address is mapped, where a memory area indicated by the memory remapping row address is in reserved space of the first memory.