Neural Processing Memory Address Remapping for Parallel ADC Use
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Solution Overview
Problem
Existing computing systems face challenges in efficiently processing large amounts of data for neural network operations due to the increased computation requirements and processor size needed for higher accuracy, leading to inefficiencies in data processing.
Innovation Solution
A data processing system with a controller, processing memory, multiplexers, and analog-to-digital converters (ADCs) that remap column addresses to distribute data storage across sub-arrays, maximizing the number of ADCs operating simultaneously, and a deserializer that reconfigures column addresses to optimize processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the computation amount and processor size are increased to improve neural network accuracy, then the inference ability is improved, but the device complexity and processing efficiency deteriorate
Solution Approach 1:
The memory is divided into multiple sub-arrays, each capable of independent data storage and processing. This segmentation allows the system to handle large computation amounts by distributing data across multiple smaller units, thereby improving neural network accuracy without proportionally increasing the complexity of a single large processor.
Solution Approach 2:
The patent introduces a column line grouping dimension, where column lines are grouped into multiple groups and further divided into segments. This dimensional organization enables efficient data distribution and parallel processing, allowing the system to achieve high accuracy through optimized data arrangement rather than simply increasing processor size.
2Measurement precision
If the computation amount is increased to improve neural network accuracy, then the inference ability is improved, but the data processing efficiency deteriorates
Solution Approach 1:
By segmenting the memory into sub-arrays and organizing column lines into groups with multiple segments, the system can process data in parallel across multiple units. This segmentation enables efficient handling of large computation amounts, maintaining high data processing efficiency while improving neural network accuracy.
Solution Approach 2:
The deserializer performs preliminary address remapping to distribute data into appropriate sub-arrays before the actual processing begins. This preliminary organization of data ensures that subsequent processing operations can proceed efficiently without requiring complex real-time address translation, thus maintaining high processing efficiency even with increased computation amounts.
3Ease of manufacture
If data is stored in a conventional manner without address remapping, then the storage process is simple, but the number of ADCs operating simultaneously is limited and processing speed is reduced
Solution Approach 1:
The system dynamically remaps column addresses based on the data storage requirements and ADC operation needs. This dynamic address remapping allows the system to optimize the number of simultaneously operating ADCs and maximize processing speed, while the deserializer handles the complexity of address translation to maintain ease of data storage.
Solution Approach 2:
The deserializer acts as an intermediary between the data storage interface and the ADC processing units. It performs address remapping and data distribution, enabling the system to maximize the number of simultaneously operating ADCs without complicating the basic storage process. The deserializer absorbs the complexity of coordinate transformation while allowing simple data storage operations.
Data Source
AI summary
A data processing system may include: a controller configured to receive a neural network processing request from a host device; a processing memory including: one or more sub arrays each including memory cells coupled between row lines and column lines; multiplexers (MUXs) provided for respective column line groups, which are configured by grouping the column lines by a preset number; and analog-to-digital converters (ADCs) coupled to the respective MUXs; and a deserializer. The deserializer is configured to receive, from the controller, data to be stored in a selected sub array and a first column address at which the data is to be stored, and remap the first column address to a second column address such that the data is distributed and stored in the memory cells coupled to the column line groups, in order to store the data in the sub array.