Semiconductor Memory Address Remapping for Channel Failure Recovery

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Solution Overview

Problem

Semiconductor memory devices face inefficiency and memory space waste due to unused channels and corresponding memory cells, as failed channels cannot be utilized for data transfer, leading to reduced performance.

Innovation Solution

The implementation of an access circuit that performs address remapping, allowing data from failed cells in one channel to be transmitted through a normal channel by converting addresses and using a channel multiplexer to connect redundant cell data lines to normal channels, thereby enabling the use of redundant cells in failed channel cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a channel is failed, then data transfer through that channel is impossible, but all memory cells in that channel become unusable, leading to memory space waste

Engineering Contradiction:
Improvechannel functionalityVSAvoidmemory space
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent segments the memory cell array into multiple channels with independent failure isolation. When one channel fails, only the cells in that specific channel are affected, while other channels remain functional. This segmentation prevents total memory loss and enables selective replacement of failed channels without affecting the entire memory array.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a channel multiplexer as an intermediary component that can dynamically route data between channels. The multiplexer allows data from a failed channel to be redirected to a functional channel, enabling indirect data transfer and preventing complete loss of memory space in the failed channel.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If redundant cells are added to replace failed cells, then memory space is wasted, but device efficiency is reduced

Engineering Contradiction:
Improvefault toleranceVSAvoiddevice efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements preliminary testing of memory cells during manufacturing to identify and mark failed cells before they are assigned to channels. This advance detection allows for proactive channel configuration and redundancy allocation, ensuring that failed cells are replaced without requiring excessive redundant cells, thus maintaining high device efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically changes the operational parameters of channels based on cell failure status. When a cell is detected as failed, the system reconfigures the channel mapping and redirects data paths to functional cells. This dynamic parameter adjustment allows the system to maintain optimal efficiency by only allocating redundancy when and where actually needed.

Inventive Principle:
Principle #35Parameter changes

3Loss of substance

If address remapping is implemented to redirect data, then memory space utilization improves, but access circuit complexity increases

Engineering Contradiction:
Improvememory space utilizationVSAvoidaccess circuit complexity
Core Design Contradiction:
Loss of substanceVSDevice complexity

Solution Approach 1:

The patent designs the channel multiplexer to serve multiple functions: it acts as a data router, an address remapper, and a channel switch. By making this single component multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby minimizing the increase in access circuit complexity while achieving effective address remapping and memory space utilization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9747058B2Semiconductor memory device, memory system including the same, and method of operating the same
Publication Date: 2017.08.29 SAMSUNG ELECTRONICS CO LTD
  • US9747058B2 patent drawing
  • US9747058B2 patent drawing
  • US9747058B2 patent drawing

AI summary

A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.