Memory Controller Address Remapping for Lower Raw Bit Error Rates
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Solution Overview
Problem
Memory sub-systems face reliability issues due to voltage differences among memory cells caused by their physical layout, leading to varying raw bit error rates (RBER) when memory access operations are performed on sequential physical addresses.
Innovation Solution
A sequencer component in the memory sub-system controller manages the distribution of page addresses and partition numbers by converting and remapping them to improve data reliability, ensuring memory access operations are not performed on sequential addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If memory access operations are performed on sequential physical addresses, then the simplicity of address management is improved, but the reliability deteriorates due to voltage differences among memory cells
Solution Approach 1:
The patent divides the memory address space into multiple segments or ranges, each mapped to different physical memory regions. Instead of sequentially accessing all addresses, the system segments the address space and distributes access operations across different partitions, thereby avoiding consecutive access to memory cells with similar voltage characteristics while maintaining manageable address handling through structured segmentation.
Solution Approach 2:
The system dynamically changes access patterns by transforming sequential address sequences into non-sequential access patterns. The controller modifies the address parameters by applying mapping functions that convert logical sequential addresses into physical non-sequential addresses, thereby changing the voltage stress profile on memory cells while preserving the logical simplicity of address management for the host system.
2Device complexity
If sequential address access is used, then the device complexity is reduced, but the raw bit error rate increases due to voltage variations
Solution Approach 1:
The patent introduces an intermediary component (the memory controller with address mapping logic) that sits between the host system and the physical memory array. This intermediary translates simple sequential addresses from the host into optimized non-sequential physical addresses, thereby shielding the host from complexity while simultaneously reducing the raw bit error rate by avoiding problematic sequential access patterns that cause voltage-induced errors.
Solution Approach 2:
The system performs preliminary address transformation before memory access operations. The controller pre-processes address sequences by applying mapping algorithms that redistribute addresses to avoid consecutive memory cell access. This preliminary action prevents voltage accumulation effects before they occur, reducing the raw bit error rate without requiring complex real-time adjustments during actual memory operations.
3Productivity
If sequential physical addresses are accessed, then the productivity is maintained, but the performance deteriorates due to varying error rates across memory cells
Solution Approach 1:
The patent implements dynamic address mapping that adapts access patterns based on real-time or pre-characterized memory cell quality metrics. Instead of static sequential access, the system dynamically selects and adjusts address sequences to avoid high-error-rate regions while maintaining high throughput. This dynamic approach preserves productivity by keeping access operations efficient while ensuring more consistent error rates across accessed memory cells.
Solution Approach 2:
The system incorporates feedback mechanisms where memory access performance and error rates are monitored, and this information is used to adjust subsequent address mapping strategies. The controller learns from access patterns and error characteristics, refining the address distribution to maintain high productivity while consistently avoiding memory regions with high error rates, thereby achieving both speed and reliability.
Data Source
AI summary
A memory access command is received. The memory access command is converted into a plurality of commands, wherein a number of commands comprised by the plurality of commands is equal to a number of partitions associated with a die of the memory device. A respective partition number and a respective page address are determined for each command of the plurality of commands. The plurality of commands is executed using, for each command of the plurality of commands, the respective partition number and the respective page address.