Non-volatile Memory Address Remapping for Yield Improvement
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Solution Overview
Problem
Conventional memory device manufacturing processes incur high costs and reduce the lifespan of memory elements due to extensive testing, which often identifies and discards 'bad' units of memory, thereby increasing the cost of high-grade memory devices and reducing their available lifetime.
Innovation Solution
Implementing physical-to-physical address remapping in a non-volatile memory module, where 'bad' units of memory are redirected to 'good' units by storing remapped addresses on an ASIC, reducing the need for extensive testing and preserving the lifespan of memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive testing is performed during manufacturing, then memory quality and reliability are improved, but production cost increases and memory element lifespan is reduced
Solution Approach 1:
The patent performs minimal preliminary testing during manufacturing to identify obviously defective units, then defers comprehensive validity testing to after packaging. This preliminary action approach reduces P/E cycles performed before the memory device reaches the consumer, thereby preserving memory element lifespan while still ensuring quality through post-packaging validation and remapping capabilities.
Solution Approach 2:
The patent introduces an address remapping table as an intermediary mechanism that redirects access from invalid memory units to valid ones. This mediator allows the system to tolerate certain defects without requiring extensive pre-screening, thus reducing manufacturing testing requirements and preserving memory element lifespan while maintaining reliability.
2Reliability
If extensive testing is performed during manufacturing, then memory quality is improved, but production cost increases
Solution Approach 1:
The patent performs only essential preliminary testing during manufacturing to identify obviously defective units, then defers comprehensive validity testing to after packaging. This reduces the number of P/E cycles performed during manufacturing, thereby lowering production costs while maintaining memory quality through post-packaging validation and remapping.
Solution Approach 2:
The patent discards only obviously defective units during manufacturing testing, then recovers potentially usable units by performing validity testing after packaging and remapping their addresses. This approach reduces manufacturing testing requirements and costs while ensuring quality by validating memory units under actual operating conditions before deployment.
3Reliability
If bad units of memory are identified and discarded, then reliability is improved, but the cost of high-grade memory devices increases
Solution Approach 1:
The patent introduces an address remapping table as an intermediary that redirects access from invalid memory units to valid ones. This allows the system to maintain high reliability without discarding potentially usable memory units, thereby reducing waste and lowering the cost of high-grade memory devices while ensuring quality through post-packaging validation.
Solution Approach 2:
The patent discards only obviously defective units during manufacturing, then recovers potentially usable units by performing validity testing after packaging and remapping their addresses. This reduces the number of units discarded, increases yield, and lowers the cost of high-grade memory devices while maintaining reliability.
4Manufacturing precision
If extensive testing is performed, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent performs only essential preliminary testing during manufacturing to identify obviously defective units, then defers comprehensive validity testing to after packaging. This reduces the time and resources spent on testing during manufacturing, thereby improving production efficiency while maintaining manufacturing precision through post-packaging validation and remapping.
Data Source
AI summary
The various embodiments described herein include systems, methods and/or devices used to enable physical-to-physical address remapping in a storage module. In one aspect, the method includes, for each of a sequence of two or more units of non-volatile memory, determining a validity state of a respective unit of memory. In accordance with a determination that the validity state of the respective unit of memory is an invalid state, the method includes storing, in a table, a second address assigned to the respective unit of memory. At least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory. In accordance with a determination that the validity state of the respective unit of memory is a valid state, the method includes forgoing assignment of the second address corresponding to the unit of memory.