Memory Address Rotation for Matrix Data Layout Optimization
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Solution Overview
Problem
Existing matrix operations in compute devices face inefficiencies due to the need for converting between row-major and column-major formats, which increases time and computational resources, or require storing matrices in both formats, leading to higher memory usage.
Innovation Solution
The proposed solution involves storing data in a manner that allows different partitions to be read consecutively, reducing sequential read operations from the same partition, and using address rotations and logical address modifications to optimize data layout and access patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If matrices are stored in both row-major and column-major formats, then matrix operations can be performed without conversion, but memory usage increases
Solution Approach 1:
The patent segments matrix data into distinct row-major and column-major storage regions within the same memory space. By dividing the storage structure into specialized segments for different access patterns, the system enables efficient row and column operations without requiring separate complete copies of the matrix, thus reducing overall memory consumption while maintaining operational speed.
Solution Approach 2:
The patent introduces a new dimension to memory addressing by implementing address rotation mechanisms that allow the same physical memory to be accessed in different dimensional orientations. This enables the system to treat the same stored data as either row-major or column-major depending on the access pattern, eliminating the need for dual format storage while maintaining fast access performance.
2Quantity of substance
If matrix conversion between row-major and column-major formats is performed, then memory usage is reduced, but time to complete matrix operations increases
Solution Approach 1:
The patent performs preliminary organization of matrix data into a unified storage structure that anticipates both row and column access patterns. By pre-arranging data in the memory with dual-access capability during the storage phase, the system eliminates the need for time-consuming format conversions during matrix operations, thus reducing operation time without requiring dual format storage.
Solution Approach 2:
The patent introduces an address rotation mechanism as an intermediary layer between the processor and memory. This intermediary translates logical row or column addresses into appropriate physical memory addresses without requiring data movement or format conversion, thereby maintaining fast access speeds while using efficient single-format storage.
3Ease of operation
If sequential read operations are performed from the same memory partition, then data access is simplified, but read delays increase
Solution Approach 1:
The patent implements dynamic address rotation that adapts based on the access pattern. When sequential reads are detected, the system dynamically rotates addresses to distribute access across different memory partitions, preventing any single partition from becoming a bottleneck. This dynamic adjustment maintains operational simplicity while significantly reducing read delays through load balancing.
Data Source
AI summary
Examples described herein relate to an apparatus comprising: circuitry to receive a request to store data as a part of a matrix in a memory device; circuitry to allocate address mappings to the data to reduce a number of sequential accesses to a same partition of a portion of the memory device; circuitry to store the address mappings for access with a read operation; and circuitry to cause storage of the data into the memory device according to the address mappings. In some examples, the matrix comprises one or more columns and/or one or more rows. In some examples, the memory device comprises one or more of: a three-dimensional (3D) cross point memory device, volatile memory device, or non-volatile memory device.