Memory Address Routing for In-Memory Processing Bandwidth
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Solution Overview
Problem
Existing semiconductor memory devices experience bottlenecks when exchanging large amounts of data with processors, particularly in applications like neural networks and IoT, due to their functional separation from processors.
Innovation Solution
An electronic device with a routing register and selection logic that maps designated memory addresses to redirected addresses, allowing PIM operations to be performed directly within the memory, thereby reducing data transfer and optimizing memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is exchanged between semiconductor memory device and processor, then processing capability is improved, but data transfer time and power consumption increase
Solution Approach 1:
The patent merges the processor and memory device into a single integrated structure where the processor is formed within the memory device package. This integration eliminates the need for external data transfer between separate components, allowing the processor to directly access and process data stored in the memory, thereby reducing data transfer time and enabling parallel processing operations.
Solution Approach 2:
The processor is nested within the memory device package, with the processor containing its own cache memory and the memory device providing additional storage capacity. This nested architecture allows data to be processed at multiple memory levels without external data movement, reducing the time required for data exchange while maintaining high processing capability.
2Productivity
If data is exchanged between semiconductor memory device and processor, then processing capability is improved, but power consumption increases
Solution Approach 1:
The integration of processor and memory device into a single package reduces power consumption by eliminating the power required for external data transfer operations. The processor can access data from the memory device's internal memory or cache without activating external communication interfaces, significantly reducing dynamic power consumption during data exchange operations.
Solution Approach 2:
The nested architecture with cache memory inside the processor and additional memory in the device package creates a hierarchical memory structure that reduces power consumption. Frequently accessed data can be kept in the processor's cache, avoiding power-intensive access to external memory, while less frequently accessed data resides in the device's internal memory.
3Device complexity
If functional separation between processor and memory is maintained, then device simplicity is preserved, but data exchange efficiency deteriorates
Solution Approach 1:
The patent combines processor and memory device functions into a single integrated package while maintaining distinct functional units. The processor handles computation tasks while the memory device provides data storage and retrieval, with direct internal connectivity between them. This integration improves data exchange efficiency through direct access paths while preserving the functional separation needed for independent operation of each component.
Data Source
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AI summary
An electronic device includes a routing register configured to store mapping information that maps each of predetermined designated memory addresses representing a partial area of a memory to a redirected memory address representing another partial area of the memory, and a selection logic configured to, when an input memory address included in a memory command received from a host processor corresponds to one of the designated memory addresses, convert the input memory address into a redirected memory address that is mapped onto the corresponding designated memory address based on the mapping information, wherein the memory command is executed at the converted redirected memory address.