Memory Address Routing Register for In-Memory Processing
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Solution Overview
Problem
The bottleneck in data exchange between semiconductor memory devices and processors, particularly in applications like neural networks and IoT, is addressed by implementing Processing-in-Memory (PIM) architecture, where arithmetic operations are performed directly within the memory.
Innovation Solution
An electronic device with a routing register and selection logic that maps designated memory addresses to redirected addresses, allowing PIM operations to be performed efficiently by converting input addresses based on stored mapping information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is exchanged between semiconductor memory device and processor, then processing capability is improved, but data exchange bottleneck increases and power consumption increases
Solution Approach 1:
The patent combines the processor and memory device into a unified PIM architecture where arithmetic operations are performed directly within the memory device. This merging eliminates the need for frequent data exchange between separate processor and memory components, thereby reducing power consumption while maintaining or improving processing capability.
Solution Approach 2:
The patent introduces a PIM controller as an intermediary component that manages arithmetic operations within the memory device. This controller coordinates between the host processor and memory operations, enabling efficient in-memory processing without requiring constant data transfer to external processors, thus reducing energy loss.
2Productivity
If PIM operations are performed on target PIM tile, then processing efficiency is improved, but routing register updates are required for next PIM tile
Solution Approach 1:
The patent pre-loads routing information into the routing register before PIM operations are executed. By preparing the routing table in advance with mappings between host addresses and PIM tile addresses, the system minimizes the time required for address translation during actual processing, thereby reducing the time loss associated with register updates.
Solution Approach 2:
The routing register is designed to be dynamically updateable, allowing the system to switch between different PIM tiles efficiently. The routing information can be modified on-the-fly to point to different target tiles as processing progresses, enabling flexible and efficient multi-tile operations without significant overhead.
Data Source
AI summary
An electronic device includes a routing register configured to store mapping information that maps each of predetermined designated memory addresses representing a partial area of a memory to a redirected memory address representing another partial area of the memory, and a selection logic configured to, when an input memory address included in a memory command received from a host processor corresponds to one of the designated memory addresses, convert the input memory address into a redirected memory address that is mapped onto the corresponding designated memory address based on the mapping information, wherein the memory command is executed at the converted redirected memory address.