Memory Module Address Mapping to Contain Row Hammer Errors
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Solution Overview
Problem
Existing error detection and correction schemes like Chipkill and SSDC/DSDD are overwhelmed by the number and distribution of errors caused by 'row hammer' in memory devices, leading to unrecoverable data loss.
Innovation Solution
Implement address mapping interconnects that permute or invert external row addresses to ensure each memory device in a module has unique neighboring rows, confining row hammer errors to a single device, making them correctible using SDDC schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row addresses are directly transmitted to memory devices without mapping, then address translation is simple and fast, but row hammer errors affect multiple neighboring rows across multiple devices overwhelming error correction schemes
Solution Approach 1:
An address mapping interconnect is introduced as an intermediary component between the memory controller and memory devices. This interconnect permutes or inverts row address bits according to a predetermined mapping scheme before transmitting addresses to memory devices, thereby confining row hammer errors to single devices while maintaining address translation functionality
Solution Approach 2:
The patent applies parameter changes by permuting or inverting specific address bits according to a predetermined mapping scheme. This transformation changes the address parameters transmitted to each memory device, ensuring that physically neighboring rows in different devices correspond to different logical row addresses, thus isolating row hammer effects
2Reliability
If error detection and correction schemes are enhanced to handle more errors, then more row hammer errors can be corrected, but the schemes become overwhelmed when errors affect multiple devices
Solution Approach 1:
The patent converts the harmful row hammer effect into a contained, correctible error by using address mapping to ensure that hammered rows in one device do not correspond to hammered rows in other devices. This transformation allows existing error correction schemes to effectively handle row hammer errors that would otherwise propagate across multiple devices
Data Source
AI summary
Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.