Non-volatile Memory Address Scramble for Read Margin
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Solution Overview
Problem
Non-volatile memory devices face challenges in maintaining consistent read margins and reducing error bits due to variations in tile activation and word/bit line bridges during read operations, leading to decreased yield and reliability.
Innovation Solution
The implementation of an address scramble method that reconfigures the activation of tiles, word lines, and bit lines during read operations, ensuring equalized read levels and minimizing error correction code consumption by distributing error bits across different tile and line configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional address mapping is used for read operations, then the memory device structure is simple, but read margin is inconsistent and error bits increase due to tile and line variations
Solution Approach 1:
The patent applies address scramble in advance during read operations to redistribute read requests across different tiles and word/bit lines. This preliminary redistribution equalizes the read levels before actual reading occurs, preventing consistent activation of the same tiles or lines that causes read margin variations and error bits.
2Reliability
If address scramble is applied to equalize read levels, then read margin improves, but control logic complexity increases
Solution Approach 1:
The control logic performs address scramble in advance during read operations to redistribute read requests across different tiles and word/bit lines. This preliminary redistribution equalizes the read levels before actual reading occurs, preventing consistent activation of the same tiles or lines that causes read margin variations and error bits.
Solution Approach 2:
The patent changes the address parameters by applying scramble functions that map logical addresses to physical addresses differently for read operations compared to write operations. This parameter transformation equalizes the distribution of read requests across memory tiles and lines, improving read margin without requiring fundamental changes to the memory structure.
3Productivity
If address scramble is used to distribute error bits, then error correction code consumption decreases, but the reading process becomes more complex
Solution Approach 1:
The control logic performs address scramble in advance during read operations to redistribute read requests across different tiles and word/bit lines. This preliminary redistribution equalizes the read levels before actual reading occurs, preventing consistent activation of the same tiles or lines that causes read margin variations and error bits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances read margin and yield by equalizing read performance across tiles and reducing the consumption of error correction codes, thereby improving the reliability and efficiency of non-volatile memory devices.
Implementation Method 1
A chalcogenide alloy may change into a crystalline state or an amorphous state after being heated and cooled. The phase change material has a low resistance in the crystalline state, and has a high resistance in the amorphous state.
Data Source
AI summary
A non-volatile memory device includes a memory cell array, a word line driver, a bit line driver, a read circuit, and control logic. The memory cell array includes a plurality of banks. Each bank includes a plurality of tiles. Each tile includes a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines. The word line driver selects one of the word lines in response to an input address. The bit line driver selects one of the bit lines in response to the input address. The read circuit reads a code word from the memory cell array in a read operation. The control logic is configured to control the word line driver, the bit line driver, the read circuit in the read operation. The control logic performs an address scramble on the input address, and provides the scrambled address to the read circuit to access the plurality of tiles in the read operation.