Non-Volatile Memory Address Data Segmentation for Speed
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Solution Overview
Problem
As memory capacity increases in NAND cell type flash memory, the volume of address data required for reading and writing data also grows, leading to slower operating speeds due to the need to specify multiple bits of data per memory cell, which complicates data transfer and processing.
Innovation Solution
A non-volatile semiconductor storage device with a memory cell array capable of storing N bits of data per cell, utilizing a controller that separates address data into a logical structure, where page data is included in commands rather than address data, allowing for efficient data access and processing without unnecessary data expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased by adding more memory cells or using multi-value storage schemes, then storage capacity is improved, but the volume of address data increases leading to slower operating speed
Solution Approach 1:
The patent segments the address data into two distinct parts: a first address data for identifying memory cell positions and a second address data for specifying page information. This segmentation allows the memory system to handle multi-value storage (N≥2 bits per cell) without increasing the volume of position-identifying address data, thereby maintaining operating speed while achieving higher storage capacity through the second address data field.
2Quantity of substance
If more memory chips are included in one module to increase capacity, then storage capacity is improved, but the data volume of address data increases leading to longer transfer time
Solution Approach 1:
By segmenting address data into position identification (first address data) and page specification (second address data), the patent enables efficient addressing in multi-chip modules. The first address data volume remains constant regardless of the number of chips, while the second address data handles page information, thus preventing address data transfer time from increasing with module capacity expansion.
3Quantity of substance
If multi-value storage scheme is adopted to store multiple bits per cell, then storage capacity is improved, but address data structure becomes more complex requiring additional page specification
Solution Approach 1:
The patent resolves the complexity issue by clearly segmenting address data into two functional parts: first address data for position identification and second address data for page specification. This structured segmentation provides a systematic method for handling multi-value storage that is easier to implement and manage compared to alternative complex addressing schemes.
Data Source
AI summary
A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell.