Memory Address Request Sorting Using Input Match Masks
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Solution Overview
Problem
In computer processor systems, the number of pending memory access requests often exceeds the maximum number of memory accesses that can be made in parallel, leading to inefficient memory access schemes due to non-unique memory address requests.
Innovation Solution
An apparatus comprising a comparator block to generate a binary classification dataset identifying unique memory addresses, and combination logic units to sort and combine bits from this dataset, ultimately producing a binary output that identifies a set of unique output memory addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple memory access requests are made in parallel to reduce latency, then memory access speed is improved, but the number of pending requests exceeds the maximum parallel access capacity, leading to inefficient access schemes
Solution Approach 1:
The patent extracts and removes duplicate memory addresses from the request list using a comparison mechanism. By identifying and eliminating redundant requests, the system ensures that only unique addresses are processed in parallel, preventing the pending request queue from exceeding parallel capacity while maintaining maximum parallelism for valid requests.
Solution Approach 2:
The patent performs preliminary comparison of memory addresses before they enter the parallel access pipeline. By pre-filtering and classifying addresses into unique and duplicate categories, the system prepares a cleaned request list that fits within parallel capacity constraints, enabling efficient parallel processing without latency penalties.
2Quantity of substance
If multiple memory access requests contain non-unique addresses, then the request volume is increased, but multiple accesses to the same address result in inefficient memory access schemes
Solution Approach 1:
The patent extracts and removes duplicate memory addresses from the request list using a comparison mechanism. By identifying and eliminating redundant requests, the system ensures that only unique addresses are processed in parallel, preventing the pending request queue from exceeding parallel capacity while maintaining maximum parallelism for valid requests.
Solution Approach 2:
The patent creates a binary classification dataset that copies the essential information about address uniqueness without duplicating the full request list. This compressed representation allows the system to track which addresses have been seen and filter duplicates efficiently, reducing the effective request volume while preserving access patterns.
3Productivity
If a sorting mechanism is implemented to identify unique memory addresses, then memory access efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the address processing into distinct functional stages: comparison phase (identifying unique addresses), classification phase (creating binary datasets), and selection phase (generating final address list). This segmentation allows each stage to be optimized independently and reduces overall complexity by breaking down the sorting task into manageable comparison operations rather than a single complex sorting algorithm.
Solution Approach 2:
The patent transforms the address data into a binary classification format, changing the representation from full address values to unique/fake flags. This parameter transformation simplifies subsequent processing by working with binary data rather than full addresses, reducing the complexity of comparison and selection operations while maintaining the ability to identify unique addresses.
Data Source
AI summary
Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing a non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a selection of bits of the binary classification dataset and sort its received selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset. Output generating logic selects between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.