Semiconductor Memory Address Storing Circuits Refresh Control
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Solution Overview
Problem
Semiconductor memory devices face data loss due to current leakage and the row hammering phenomenon, which requires frequent refresh operations to maintain data accuracy, leading to inefficiencies and potential word line disturbances.
Innovation Solution
A semiconductor memory device with a random sampling circuit, address storing circuits, and a duplication decision circuit that prevents duplicated addresses from being stored and performs targeted refresh operations based on randomly sampled addresses, reducing unnecessary refreshes and minimizing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal refresh operations are performed on all word lines at predetermined periods, then data loss due to current leakage is prevented, but refresh operation efficiency is reduced due to unnecessary refreshes
Solution Approach 1:
The patent applies partial action by performing refresh operations only on sampled word lines rather than all word lines. The sampling circuit selects specific word lines based on activation history, and only these sampled word lines undergo refresh operations. This reduces the total number of refresh operations while still preventing data loss on frequently accessed word lines, thereby improving refresh efficiency without sacrificing data retention reliability.
2Object-affected harmful factors
If target refresh operations are performed on frequently activated word lines to prevent row hammering, then word line disturbance is reduced, but device complexity increases due to additional sampling and decision circuits
Solution Approach 1:
The patent segments the refresh operation into two distinct parts: normal refresh operations that periodically refresh all word lines to prevent data loss, and target refresh operations that specifically refresh sampled word lines to prevent row hammering. This segmentation allows each refresh type to address its specific problem independently, reducing word line disturbance from row hammering while maintaining data retention through normal refreshes.
Solution Approach 2:
The patent applies preliminary action by using a sampling circuit to identify and store addresses of frequently activated word lines before row hammering occurs. The sampling circuit continuously monitors word line activation and pre-identifies vulnerable word lines, allowing the system to perform targeted refresh operations in advance to prevent data distortion, rather than waiting for row hammering to occur.
3Ease of manufacture
If sampling addresses are stored in address storing circuits without duplication check, then address storing simplicity is maintained, but refresh operation accuracy is reduced due to duplicated addresses
Solution Approach 1:
The patent applies feedback by implementing a duplication check mechanism that compares newly sampled addresses against previously stored addresses in the address storing circuits. Before storing a new sampling address, the system checks whether it already exists in the address storing circuits. This feedback loop ensures address uniqueness, improving refresh operation accuracy by preventing duplicate refresh operations on the same word line, while maintaining relatively simple circuit implementation through efficient comparison logic.
Data Source
AI summary
A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits suitable for sequentially storing a sampling address as one of a plurality of latch addresses, and sequentially outputting each of the latch addresses as a target address according to a refresh command; a duplication decision circuit suitable for preventing the sampling address from being stored in the address storing circuits when the sampling address is identical to any of the latch addresses stored in the address storing circuits; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to the refresh command.