Memory Device Address-Table Buffering for Gapless Data Transfer
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Solution Overview
Problem
Memory devices face challenges in providing high data storage capacity and bandwidth while minimizing standby power consumption, particularly due to the inability of clock domain separation to enable gapless data communication.
Innovation Solution
The implementation of a memory device with a command/address decoder that includes a buffer memory and decoding logic circuits to store and synchronize an address table, allowing for table-based commands and index information processing, along with a memory controller that generates and updates synchronization commands to manage sub-tables across multiple volatile memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If increased operating frequency is used to provide high data storage capacity and bandwidth, then data storage capacity and bandwidth are improved, but standby power consumption increases
Solution Approach 1:
The memory device performs preliminary actions by storing an address table locally and synchronizing it with the memory controller before actual data operations. This allows the memory device to autonomously decode commands using the pre-stored address table, reducing the need for continuous high-frequency operations and thereby lowering standby power consumption while maintaining high data storage capacity and bandwidth during active operations
2Use of energy by moving object
If clock domain separation is introduced to reduce standby power consumption, then standby power consumption is reduced, but gapless data communication cannot be achieved
Solution Approach 1:
The address table serves as an intermediary mechanism between the memory controller and memory device. It enables synchronization and coordination between different clock domains by providing a shared reference structure that both sides can access and update, thereby maintaining gapless data communication while allowing clock domain separation to reduce standby power consumption
3Productivity
If address table synchronization is implemented to improve performance and bandwidth, then data communication efficiency is improved, but device complexity increases
Solution Approach 1:
The address table is segmented into manageable structures that can be stored in the buffer memory of the memory device and synchronized with the memory controller. This segmentation allows for efficient updates and maintenance of the address table without requiring complex synchronization protocols, thereby improving data communication efficiency while keeping device complexity manageable
Data Source
AI summary
A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.