Arithmetic-Based Memory Address Translation for Chip Kill Recovery
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Solution Overview
Problem
Existing memory systems face high latency and resource exhaustion due to complex division operations required for address translation, especially when implementing chip kill capabilities for data protection and recovery.
Innovation Solution
Implement memory address translation using simpler arithmetic operations such as addition and subtraction, eliminating the need for complex division operations and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex division operations are used for address translation to ensure accurate data mapping, then data protection and recovery accuracy is improved, but latency and resource consumption increase
Solution Approach 1:
The patent changes the mathematical parameters of the address translation operation from division to multiplication and addition/subtraction. Specifically, it uses the relationship between stripe size and channel number to transform the division operation into equivalent multiplication by pre-calculated constants followed by bitwise operations, maintaining accuracy while reducing computational complexity and latency
Solution Approach 2:
The patent replaces the mechanical division operation with a combination of multiplication and bitwise shift operations. By pre-calculating multiplication factors based on stripe size and channel configuration, the system substitutes complex division mechanics with simpler arithmetic operations that can be executed faster in hardware
2Reliability
If complex division operations are used for address translation to maintain proper data striping, then data protection capability is improved, but device complexity increases
Solution Approach 1:
The patent transforms the operational parameters from division-based calculations to multiplication-based calculations with bitwise operations. This parameter change simplifies the hardware circuitry required for address translation while maintaining the ability to properly map addresses across striped data and ECC regions for data protection
Solution Approach 2:
The patent performs preliminary calculations of multiplication factors and shift amounts during system initialization or configuration, storing these pre-computed values for use during address translation. This preliminary action eliminates the need for complex division circuits during runtime, reducing device complexity while maintaining data protection capabilities
3Measurement precision
If complex division operations are used for address translation to ensure proper ECC data mapping, then data recovery accuracy is improved, but resource consumption increases
Solution Approach 1:
The patent changes the computational parameters from division operations to multiplication and bitwise operations, which are less resource-intensive. The pre-calculated multiplication factors enable accurate ECC data mapping through simpler arithmetic that consumes fewer computational resources and energy
Solution Approach 2:
The patent substitutes energy-intensive division operations with lower-power multiplication and bitwise shift operations in the address translation logic. This substitution reduces computational resource consumption while maintaining the precision required for accurate ECC data mapping and recovery
Data Source
AI summary
Address translation of host commands to access host data stored in memory devices that provides a chip kill capability not only involves locating where the host data is stored, but also involves locating where parity data striped with the host data is stored. In locating where the parity data is stored, the address translation can be performed with logical (e.g., arithmetic) operations.