Memory Address Translation Asynchronous Maintenance
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Solution Overview
Problem
Current memory address translation systems face inefficiencies in handling multiple virtual machines and large memory storage, particularly in asynchronous maintenance operations, where maintenance can stall processors and lead to conflicts and increased latency.
Innovation Solution
The proposed solution involves a memory address translation apparatus with a page table access circuitry, a translation data buffer, and control circuitry that allows for asynchronous retrieval of translation data, enabling simultaneous processing of lookup and maintenance operations. This apparatus uses a maintenance queue to perform maintenance operations asynchronously, preventing stalls and conflicts by initiating page table walks early and using a fill queue to prioritize overlapping maintenance operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronous maintenance operations are used, then data consistency is maintained, but processor stalls occur and latency increases
Solution Approach 1:
The patent implements preliminary action by initiating page table walks in advance before the translation data buffer is fully updated. The control circuitry starts the page table walk process before the TLB flush completes, allowing the translation data to be prepared ahead of time. This eliminates processor stalls by having the maintenance operation ready to execute immediately when needed, while maintaining data consistency through proper sequencing of the buffer update and walk initiation.
2Reliability
If translation data buffer is updated synchronously, then data integrity is ensured, but maintenance operations cannot proceed in parallel
Solution Approach 1:
The patent applies segmentation by dividing the maintenance operation into distinct phases: a first phase that updates the translation data buffer, and a second phase that initiates page table walks. This segmentation allows the buffer update and the walk initiation to occur in separate, non-blocking phases. The control circuitry manages these phases independently, enabling parallel processing while maintaining data integrity through proper phase sequencing and completion signals.
3Speed
If page table walks are initiated immediately, then translation speed increases, but conflicts with ongoing buffer updates occur
Solution Approach 1:
The patent implements feedback by using completion signals to coordinate between the buffer update process and the page table walk initiation. The control circuitry monitors the completion of the buffer update phase and uses this feedback to determine when to safely initiate the page table walk. This feedback mechanism ensures that walks are started only when the buffer is in a consistent state, preventing conflicts while maintaining high translation speed through efficient overlap of operations.
4Device complexity
If single-stage translation is used, then device complexity is reduced, but security isolation between virtual machines is insufficient
Solution Approach 1:
The patent applies segmentation to the translation process by implementing a two-stage translation architecture. The first stage handles virtual-to-intermediate translation with security isolation, while the second stage handles intermediate-to-physical translation. This segmentation allows each stage to be optimized independently: the first stage provides strong security isolation between virtual machines, while the second stage can proceed in parallel without increasing overall complexity, as the stages are coordinated through the control circuitry.
Data Source
AI summary
Memory address translation apparatus comprises page table access circuitry to access page table data to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the virtual address space, one or more instances of the translation data; and control circuitry, responsive to an input initial memory address to be translated, to request retrieval of translation data for the input initial memory address from the translation data buffer and, before completion of processing of the request for retrieval from the translation data buffer, to initiate retrieval of translation data for the input initial memory address by the page table access circuitry.