Memory Address Translation Using Variable-Size Translation Buffer
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Solution Overview
Problem
Current memory address translation techniques, such as page table walks, suffer from latency and high processing requirements, and lack efficient methods for handling variable-sized regions of virtual memory address spaces.
Innovation Solution
The proposed solution involves a memory address translation apparatus with a translation data store that stores instances of translation data defining address range boundary values, a detector circuitry to identify the appropriate instance for a given virtual memory address, and translation circuitry to apply the corresponding translation, allowing for efficient translation between virtual and output memory addresses by retrieving additional instances when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If page table walks are used for memory address translation, then complete address translation can be achieved, but latency increases and processing requirements become high
Solution Approach 1:
The patent segments the address translation process into two distinct stages: a fast path using a translation buffer (TB) for common cases, and a slow path using page table walks for exceptional cases. This segmentation allows the system to achieve complete address translation reliability while minimizing latency for the majority of translations that can be handled by the TB.
Solution Approach 2:
The translation buffer (TB) is pre-loaded with translation information before it is needed, allowing common address translations to be resolved immediately without performing a full page table walk. This preliminary action stores frequently accessed translation data in advance, reducing the latency for subsequent translations.
2Device complexity
If fixed-size page table entries are used, then translation structure is simplified, but efficiency for variable-sized regions is reduced
Solution Approach 1:
The patent implements dynamic entry sizes in the translation buffer (TB), allowing each entry to be customized according to the specific region it covers. This enables efficient handling of variable-sized memory regions while maintaining a relatively simple overall translation structure. The TB can accommodate different entry sizes without requiring a completely complex hierarchical structure.
3Loss of time
If translation buffer is used for fast translation, then latency is reduced, but handling of addresses outside buffer requires additional retrieval operations
Solution Approach 1:
The patent extracts and handles the exceptional case (addresses not in TB) separately from the common case. When an address is not found in the translation buffer, the system performs a page table walk to retrieve the necessary translation data and populate the TB for future use. This extraction approach minimizes the impact on overall latency by isolating the more complex retrieval operations to only when necessary.
Data Source
AI summary
A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.