Memory Address Translation Using Segmented Logical Addresses
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Solution Overview
Problem
Existing memory architectures face complexity and speed issues when mapping logical addresses to physical addresses in systems with an arbitrary number of physical memory units, particularly when the number is not a power of two, leading to costly and slow division circuits.
Innovation Solution
A method and apparatus that perform address translation in memory systems with a plurality of memory streaming units by using a modulo operation on less than all bits of the logical address to determine the corresponding physical address, incorporating striped and non-striped regions, and employing local and magic blocks to optimize the translation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional modulo operation is used to map logical address to physical address in memory with arbitrary number of physical units, then the mapping can be performed, but the division circuit becomes costly and slow
Solution Approach 1:
The logical address is divided into two parts: a first portion used to identify the physical memory device and a second portion used for the address within that device. This segmentation allows the modulo operation to be performed on only the first portion rather than the entire logical address, significantly reducing the complexity and cost of the division circuit while maintaining correct mapping functionality.
2Ease of manufacture
If the number of physical memory storage devices is reduced from a power of two to an arbitrary number, then cost and chip area are reduced, but the mapping complexity increases due to costly division circuits
Solution Approach 1:
By segmenting the logical address into a device identifier portion and an intra-device address portion, the system enables arbitrary numbers of memory devices (not restricted to powers of two) while avoiding complex division circuits. The mapping logic uses the segmented address with simplified operations to achieve both cost reduction and manageable complexity.
Solution Approach 2:
The invention changes the parameter of the modulo operation from operating on all K bits of the logical address to operating on only a subset (the first portion) of the logical address. This parameter change reduces the operational complexity while still achieving correct device identification for arbitrary numbers of memory devices.
3Measurement precision
If modulo operation is performed on all bits of logical address, then accurate physical address mapping is achieved, but the operation becomes more costly and slower
Solution Approach 1:
The logical address is segmented such that only the necessary portion (first portion) is used for device identification via modulo operation, while the second portion is directly used for the address within the device. This segmentation achieves accurate mapping without the time penalty of performing modulo operations on the entire logical address.
Solution Approach 2:
The invention extracts only the necessary bits (first portion of logical address) required for device identification and performs the modulo operation solely on these extracted bits. This extraction approach maintains mapping accuracy while significantly reducing the computational time and resources required compared to operating on all bits.
Data Source
AI summary
A method for address translation in a memory comprising a plurality of memory streaming units (MSUs), wherein n represents the number of MSUs and n is not a power of two, and wherein the memory further comprises a striped region, the method comprising determining an MSU from among the plurality of MSUs having a physical address (PA) in the striped region corresponding to a logical address (LA) comprising performing a modulo n operation on less than all the bits representing the LA; and transmitting the LA to the MSU.