Memory Address Uniqueness Testing via Current Mirror Comparison
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Solution Overview
Problem
Conventional address uniqueness testing methods for memory devices are time-consuming and inefficient, particularly for high-density non-volatile memories, due to limitations in testing speed and parallel operation, and are prone to errors caused by silicon defects in the address path.
Innovation Solution
A circuit and method utilizing current sinks and current mirror transistors to compare total current from word lines with a reference current, generating test pass or fail indications, which includes current-to-voltage amplifiers and logic gates to determine address uniqueness status in a time-efficient manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional address uniqueness testing methods are used, then testing coverage is achieved, but testing time is excessive
Solution Approach 1:
The invention extracts the address uniqueness testing function from the memory array access operations. By using current sinks coupled to word lines and comparing total current with a reference current, the test isolates address path functionality from memory cell operations, achieving faster testing without sacrificing reliability
Solution Approach 2:
The invention replaces the mechanical/sequential operations of writing and reading memory cells with an electrical current comparison mechanism. The current mirror circuit and comparator enable parallel evaluation of address uniqueness through electrical signals rather than sequential memory access operations
2Reliability
If memory array access is performed for testing, then address uniqueness is verified, but silicon area is consumed and test errors may occur
Solution Approach 1:
The invention extracts the testing function from the memory array itself, using separate current sink circuits coupled to word lines. This externalizes the testing mechanism, avoiding consumption of memory cell storage space while maintaining test accuracy through direct electrical measurement of address line states
3Speed
If conventional sequential testing methods are used, then testing thoroughness is maintained, but testing speed is limited
Solution Approach 1:
The invention merges multiple address line states into a single total current measurement through current sinks. The current mirror circuit combines information from all word lines simultaneously, enabling parallel evaluation that increases speed while the integrated comparator keeps circuit complexity manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces testing time for address uniqueness, supporting high-density memory devices by enhancing testing speed and accuracy, while avoiding access to the memory array to prevent test errors and conserve silicon area.
Implementation Method 1
A current mirror circuit is coupled to the plurality of current sinks and a circuit output node is coupled to the current mirror circuit
Implementation Method 2
The plurality of current sinks includes a plurality of current mirror transistors configured in paired series, and wherein a first transistor of the current mirror transistor includes a gate coupled to a gate of a bias transistor
Data Source
AI summary
A circuit and method for testing address uniqueness of a memory array are disclosed. The circuit includes a plurality of current sinks associated with rows and columns of the memory array. A plurality of word lines of the memory array are coupled to the plurality of current sinks. A current mirror circuit is coupled to the plurality of current sinks and a circuit output node is coupled to the current mirror circuit. The circuit output node is configured to compare a total current from tested word lines of the memory array with a predetermined reference current, and to output a test pass or test fail indication in response to the comparison.