Memory Address Verification for Special Handling Metadata Detection

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Solution Overview

Problem

Conventional memory subsystems face inefficiencies in managing special handling metadata, leading to increased metadata processing and read latency due to separate handling of host data structures and the consumption of space that could be used for other data or error correction.

Innovation Solution

The solution involves using address verification to detect special handling metadata by flipping bits of the logical block address (LBA) to create a masked LBA, which reduces firmware processing and allows for the identification of special handling metadata, thereby freeing up space and reducing read latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate handling of host data structures with special handling metadata is implemented, then data integrity is ensured, but metadata processing time increases

Engineering Contradiction:

Improvedata integrityVSAvoidmetadata processing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent combines special handling metadata with regular address verification metadata by storing both types of information in the same metadata structures. This merging eliminates separate processing paths for special handling data, thereby reducing metadata processing time while maintaining data integrity through unified verification.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The address verification metadata structure is designed to serve multiple functions: it verifies addresses for all host data structures and simultaneously indicates special handling requirements. This multi-functionality reduces the need for separate metadata processing while ensuring data integrity through comprehensive verification.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If special handling metadata is stored separately, then data integrity is maintained, but available space for error correction and other data decreases

Engineering Contradiction:

Improvedata integrityVSAvoidavailable space for error correction

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent merges special handling metadata into the existing address verification metadata structures, eliminating the need for separate storage allocation. This consolidation frees up space that can be reallocated to error correction codes and other critical data functions while maintaining data integrity through integrated verification.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent recovers storage space by eliminating redundant separate metadata structures for special handling data. The space previously allocated for separate special handling metadata is now available for error correction and other data functions, while data integrity is maintained through the integrated address verification system.

Inventive Principle:

Principle #34Discarding and recovering

3Reliability

If conventional separate metadata handling is used, then all metadata can be tracked, but read operation latency increases

Engineering Contradiction:

Improvemetadata tracking completenessVSAvoidread operation latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent combines special handling metadata with address verification metadata into unified structures, allowing the memory subsystem to track all metadata in a single integrated system. This merging enables parallel processing and eliminates sequential handling steps, thereby reducing read operation latency while maintaining complete metadata tracking.

Inventive Principle:

Principle #5Merging (Combining)

4Loss of time

If address verification is enhanced to detect special handling metadata, then read latency is reduced, but firmware processing complexity increases

Engineering Contradiction:

Improveread latencyVSAvoidfirmware processing complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent uses bit-flipped copies of logical block addresses as address verification values to encode special handling metadata. This copying approach allows the firmware to detect special handling conditions through simple bit comparison operations, reducing processing complexity while maintaining fast read operations.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent transforms address verification by applying bit-flipping operations to create encoded addresses that contain special handling information. This parameter change converts metadata detection into a simple bitwise operation, reducing firmware processing complexity while enabling fast read latency through efficient detection mechanisms.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11372716B2Detecting special handling metadata using address verification

Publication Date: 2022.06.28 MICRON TECHNOLOGY INC

AI summary

Exemplary methods, apparatuses, and systems include receiving a read request directed to an addressable unit of memory. The read request includes an address for the addressable unit and the addressable unit includes a metadata portion. A mismatch between one or more bits of the address in the read request and a corresponding one or more bits of an address verification value in the metadata portion of the addressable unit is detected. A position of each of the one or more bits that did not match is determined to be an indication of special handling for the addressable unit of memory. In response to the indication of special handling, special handling metadata for the addressable unit of memory is read and the read request is processed according to the special handling metadata.