Memory Address Error Detection to Cancel Erroneous Writes
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Solution Overview
Problem
Modern memory systems face significant challenges in error detection and correction, particularly as data transfer rates increase, leading to issues with signal quality due to noise and other factors, where address errors can be more detrimental than data errors, potentially corrupting stored data.
Innovation Solution
The implementation of a mechanism in memory systems where DRAM computes an error-detection code (EDC) based on both address and data, which is then verified by the memory controller, allowing for timely detection and prevention of erroneous write operations, thereby ensuring error-resistant transmission of both address and data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then transmission errors increase due to noise and signal quality degradation
Solution Approach 1:
The patent applies preliminary action by computing the error-detection code (EDC) based on the address before the write operation is executed. This allows the memory controller to verify the address integrity in advance, detect potential errors before they cause data corruption, and cancel erroneous write commands proactively, thereby maintaining reliability at high transfer rates
2Reliability
If error detection mechanism is implemented to improve reliability, then latency increases due to additional verification steps
Solution Approach 1:
The EDC computation is performed preliminarily based on the address alone, before data arrives and before the write operation executes. This preliminary verification minimizes latency by catching address errors early in the pipeline, allowing erroneous operations to be cancelled without waiting for data transfer to complete
Solution Approach 2:
The error detection is segmented into address-based EDC computation separate from data transfer. This allows independent verification of address integrity without blocking the data path, reducing overall latency while maintaining reliability
3Reliability
If address errors are detected to prevent data corruption, then data buffering increases to allow error verification
Solution Approach 1:
The patent performs preliminary error detection on the address before data is buffered for write operations. By computing the EDC based on the address in advance and verifying it before data arrives, the system can cancel erroneous write commands without needing to buffer the data, thus preventing data corruption while minimizing buffering requirements
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.