Memory Address Error Detection With Write Cancellation
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Solution Overview
Problem
Modern memory systems face significant challenges in error detection and correction, particularly as data transfer rates increase, leading to issues with signal quality due to noise and other factors, where address errors can be more detrimental than data errors, potentially corrupting stored data.
Innovation Solution
A mechanism is implemented in memory systems where the DRAM computes an error-detection code (EDC) based on both address and data, which is then verified by the memory controller, allowing for timely detection and correction of errors, including the ability to cancel erroneous write commands and optimize system latency and buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then transmission errors increase due to noise and signal quality degradation
Solution Approach 1:
The patent applies preliminary action by computing error-detection codes (EDC) for both address and data before transmission occurs. The memory controller calculates EDC values for the address and data portions separately, then transmits them to the memory device. This allows error detection capabilities to be built into the transmission process beforehand, enabling the system to maintain higher data transfer rates while having mechanisms ready to detect and handle errors that may occur due to noise and signal degradation.
2Reliability
If error detection mechanisms are added to improve reliability, then device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error detection process into separate components: the memory controller computes EDC values for address and data portions separately, transmits them independently, and the memory device verifies them separately. This segmented approach allows error detection functionality to be distributed across existing components rather than requiring a monolithic complex error detection system, thereby improving reliability while managing device complexity through modular organization of error detection tasks.
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.