Nonvolatile Memory Address Mapping for Parallel Write Updates

The patent applies preliminary action by updating the address translation table before the data write operation is fully completed. The controller determines physical addresses and updates the translation table in advance, while the actual data transfer and write operations proceed in parallel. This resolves the contradiction by ensuring the translation table is ready (maintaining reliability) while not blocking the write performance, as both operations can overlap in execution.

The patent implements continuity of useful action by overlapping the address translation table update with the data transfer and write operations. Instead of completing one operation before starting the next, the system maintains continuous productive activity by executing multiple operations in parallel. The controller updates the translation table while simultaneously transferring and writing data, maximizing resource utilization and eliminating idle time, thus improving write performance without compromising data integrity.

The patent applies preliminary action by performing the address translation table update in advance, before the data write operation completes. This allows the update to be scheduled and executed at a convenient time without rushing the calculation, maintaining adequate update speed while avoiding the need for excessive computational resources. The translation work is prepared beforehand, reducing the peak calculation demand during critical write operations.

The patent implements continuity of useful action by executing the address translation table update in parallel with data transfer and write operations. This overlapping approach distributes the computational load over time rather than concentrating it in a single high-intensity burst, reducing peak power consumption and allowing simpler, more power-efficient hardware to handle the translation tasks without compromising overall update speed.