Memory-Addressed Maps for Persistent Storage Bypassing NVMe
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Solution Overview
Problem
Current storage systems, such as solid-state drives (SSDs), face challenges in efficiently managing memory access and providing direct persistent storage access to peer devices without relying on block storage protocols like NVMe, especially when dealing with non-volatile memory technologies like NAND or 3D crosspoint memory.
Innovation Solution
The implementation of memory-addressed device (MAD) technology that maps memory space to non-volatile storage, enabling direct memory-mapped input/output operations within the PCIe memory space, allowing peer-to-peer access and bypassing the need for block I/O command protocols, with features like I/O buffering and synchronization to ensure data persistence and ordering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If block storage protocols like NVMe are used for SSD access, then standardized storage access is achieved, but peer-to-peer direct access without host CPU involvement is limited
Solution Approach 1:
The patent introduces a memory-mapped I/O interface as an intermediary between peer devices and the non-volatile storage media. This interface enables direct access by translating peer device requests into storage operations without requiring host CPU involvement or block storage protocols, thus resolving the contradiction between ease of peer-to-peer access and protocol overhead complexity
Solution Approach 2:
The system enables peer devices to directly access storage media through memory-mapped I/O regions, allowing devices to service their own storage needs without host CPU mediation. This self-service capability eliminates the need for host software management of NVMe protocols, reducing protocol overhead while maintaining standardized access
2Speed
If memory space is mapped directly to non-volatile storage, then access speed improves, but data persistence and ordering guarantees become more challenging
Solution Approach 1:
The patent implements preliminary actions through I/O buffering and synchronization mechanisms that prepare and validate data before it is written to non-volatile storage. These preliminary actions ensure data persistence and ordering guarantees are established before the high-speed memory-mapped access completes, resolving the contradiction between access speed and reliability
Solution Approach 2:
The system incorporates feedback mechanisms through synchronization operations that confirm data has been successfully persisted to storage. This feedback loop ensures that despite the high speed of memory-mapped access, reliability guarantees for data persistence and ordering are maintained through verification
3Reliability
If host CPU is involved in storage management, then protocol compliance is ensured, but performance overhead increases
Solution Approach 1:
The patent extracts the protocol compliance function from the host CPU and relocates it to dedicated logic within the storage device. This extraction allows protocol compliance to be maintained through hardware-enforced rules rather than CPU software, eliminating performance overhead while ensuring reliability
Solution Approach 2:
The system replaces the mechanical system of CPU software-based protocol management with a hardware-based memory-mapped I/O interface that enforces protocol compliance through dedicated logic circuits. This substitution maintains reliability while dramatically improving productivity by eliminating CPU involvement in storage access operations
Data Source
AI summary
An embodiment of a semiconductor apparatus may include technology to determine one or more logical block addresses for a persistent storage media, determine one or more addresses for a physical memory space, and define a memory-mapped input/output region for the physical memory space with a direct mapping between the one or more addresses for the physical memory space and the one or more logical block addresses for the persistent storage media. Other embodiments are disclosed and claimed.