Memory Error Correction Circuit for Adjacent Bit Faults
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Solution Overview
Problem
Conventional techniques are inadequate for correcting all errors in memory, particularly as transistor dimensions decrease, leading to issues with data corruption in integrated circuits, which can render them unusable until correct data is restored.
Innovation Solution
A method and circuit for correcting adjacent bit errors in memory by determining and correcting single errors in memory cells using parity bits and error correction codes, allowing for continuous operation without reloading entire memory frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction techniques are used, then single bit errors can be detected and corrected, but multiple adjacent bit errors cannot be corrected
Solution Approach 1:
The memory is divided into multiple banks, and parity bits are separately generated for different sets of memory cells (e.g., even and odd columns). This segmentation allows the system to track errors in different regions independently, enabling detection and correction of adjacent bit errors that would otherwise be indistinguishable from single bit errors in conventional systems.
Solution Approach 2:
The patent extends error correction from a single-dimension approach (conventional SECDED correcting any single bit) to a multi-dimensional approach by implementing separate parity tracking for different memory cell sets (e.g., column-based parity bits p1, p2, p4). This dimensional extension allows the system to distinguish between errors occurring in different dimensions, enabling correction of adjacent errors.
2Reliability
If complete memory reloading is performed to restore correct data, then data corruption is resolved, but system uptime is significantly reduced
Solution Approach 1:
Parity bits are pre-calculated and stored alongside the data in memory. When an error occurs, these pre-computed parity bits enable immediate error detection and correction without requiring complete memory reloading. The correction process only affects the specific erroneous bit(s), allowing the system to maintain continuous operation with minimal interruption.
Solution Approach 2:
The patent extracts and corrects only the specific erroneous bits from the memory using parity comparison, rather than reloading the entire memory frame. By identifying the exact location of errors through parity bit mismatches and correcting only those specific cells, the system restores data integrity while maintaining system uptime.
3Quantity of substance
If transistor dimensions are decreased to increase memory density, then more data can be stored, but error susceptibility increases
Solution Approach 1:
The patent implements a comprehensive error protection mechanism using multiple parity bits (p1, p2, p4) that are calculated and stored in advance. This cushioning layer of redundancy protects the high-density memory against errors that become more susceptible with smaller transistor dimensions, allowing the system to maintain reliability despite increased error rates from miniaturization.
Data Source
AI summary
A method of correcting adjacent bit errors in a memory is disclosed. The method comprises determining that there are errors in each set of two non-overlapping sets of the memory; changing a stored value of a memory cell of the memory until it is determined that a single error exists in the memory; identifying a location of the single error in the memory; and correcting the single error in the memory. A circuit for detecting adjacent bit errors in a memory having alternating even memory cells and odd memory cells is also disclosed.