Memory Aggregation Device Using Shared FIFO and Interconnection Matrices
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Solution Overview
Problem
High-speed hardware systems face inefficiencies due to the need for multiple FIFOs and separate memories, leading to memory waste and reduced throughput in aggregating and retrieving data streams.
Innovation Solution
A single aggregator FIFO system utilizing a shared memory with an interconnection mechanism, including input and output matrices controlled by a memory controller, operates in a round-robin manner to distribute and retrieve data streams efficiently, behaving like a single FIFO.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple separate FIFO memories are used to aggregate input data streams, then data can be stored and retrieved efficiently, but memory area on the chip is wasted due to non-shared memories
Solution Approach 1:
The patent merges multiple separate FIFO memories into a single shared memory structure. The aggregator FIFO consolidates what would otherwise be separate memory resources, allowing multiple input data streams to share the same physical memory area. This eliminates the waste of having dedicated separate memories for each stream while maintaining the ability to efficiently aggregate and retrieve data.
Solution Approach 2:
The shared memory structure serves multiple functions simultaneously - it acts as storage for multiple different input data streams, provides aggregation capability, and enables retrieval to multiple output streams. This universal memory resource replaces what would have been multiple specialized FIFO memories, optimizing chip area while maintaining productivity.
2Adaptability or versatility
If multiple separate FIFO memories are used, then data streams can be processed independently, but throughput is reduced due to lack of sharing
Solution Approach 1:
The patent implements dynamic control of the shared memory through a controller that manages data flow from multiple inputs and to multiple outputs. The system can dynamically allocate memory resources and control data retrieval based on current traffic conditions, maintaining processing independence while optimizing throughput through coordinated access to the shared memory structure.
3Area of stationary object
If a single shared memory is used for all FIFOs, then memory area is optimized, but complexity of controlling data distribution increases
Solution Approach 1:
The patent introduces a controller as an intermediary between the multiple input data streams and the shared memory, and between the shared memory and output streams. This mediator manages the complexity of data distribution by coordinating access to the shared resource, handling the logic of which data goes where, thereby optimizing memory area while managing control complexity through a centralized control mechanism.
Data Source
AI summary
The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.