Semiconductor Memory Device Air Gap Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices face reduced writing speed due to parasitic capacitance between word lines and selecting gate transistors, which cannot be effectively reduced by existing air gap formation methods when the spacing between selecting gate transistors and word lines is large.
Innovation Solution
The semiconductor memory device incorporates a method of forming cavities between word lines and selecting transistors, using a sequence of insulating films and nitride films to create side wall films and expose specific surfaces, allowing for the reduction of parasitic capacitance and improved writing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the spacing between selecting gate transistor and word line is increased to prevent abnormal cutoff and secure alignment tolerance, then reliability and manufacturability are improved, but parasitic capacitance cannot be reduced and writing speed deteriorates
Solution Approach 1:
The patent applies different structures to different regions: between word lines, oxide films are deposited to reduce parasitic capacitance, while between selecting gate transistors and end WLs, air gaps are formed to prevent abnormal cutoff. This localized differentiation resolves the contradiction by optimizing each region for its specific function.
Solution Approach 2:
The patent segments the spacing region into two distinct types: regions between adjacent word lines filled with oxide films, and regions between selecting gate transistors and end WLs filled with air gaps. This segmentation allows each region to be optimized independently, preventing abnormal cutoff while reducing parasitic capacitance in appropriate locations.
2Speed
If conventional air gap formation method is applied to reduce parasitic capacitance, then writing speed is improved, but it becomes impossible to form air gap when spacing between selecting gate transistor and end WL is large
Solution Approach 1:
The patent uses a side wall film as an intermediary structure to enable air gap formation in regions with large spacing. The side wall film is formed on the end WL, and its thickness is controlled to be not more than the spacing between the end WL and selecting gate transistor, allowing air gaps to be successfully formed even when spacing is large.
Solution Approach 2:
The patent changes the parameter of side wall film thickness to match the spacing conditions. By controlling the side wall film thickness to be not more than the spacing between end WL and selecting gate transistor, the method adapts to different spacing conditions, enabling air gap formation across various design scenarios.
3Speed
If oxide film is deposited between word lines to reduce parasitic capacitance, then writing speed is improved, but filling ability requirements become more stringent
Solution Approach 1:
The patent employs oxide films with specific properties for filling between word lines. The oxide films are deposited to completely fill the spaces between adjacent word lines, creating a consistent dielectric layer that reduces parasitic capacitance while accommodating the manufacturing requirements through proper material selection and deposition control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, increases writing speed, and prevents abnormal cutoffs by creating air gaps between word lines and selecting transistors, enhancing the performance and reliability of semiconductor memory devices.
Implementation Method 1
a nitride film is formed on the first oxide film to fill a space between each pair of adjacent ones of the word lines with the nitride film
Implementation Method 2
a first insulating film, a charge accumulating layer, a second insulating film, and a controlling gate electrode stacked in sequence
Implementation Method 3
parasitic capacitance generated between floating gate electrodes of adjacent word lines or between a floating gate and a diffusion layer reduces writing speed
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air.