3D Semiconductor Memory Air-Gap Layout for Lower Capacitance
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration and reducing process complexity while maintaining memory cell characteristics, particularly in minimizing sheet resistance and capacitance to prevent read disturbance and data write issues.
Innovation Solution
The implementation involves a semiconductor memory device with a structure that includes lower and upper lines intersecting over a substrate, with memory cells positioned between them and an air gap formed between the upper lines to reduce capacitance and sheet resistance, using a method that involves etching conductive layers and forming insulating layers to create a stacked structure with air gaps between the upper lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor memory structures are used without air gaps, then manufacturing process is simpler, but sheet resistance and capacitance are higher causing read disturbance and data write issues
Solution Approach 1:
The patent introduces air gaps (void spaces) between upper lines and between stacked structures, creating a porous-like structure that reduces parasitic capacitance and sheet resistance. The air gaps are formed by removing sacrificial layers or by controlling deposition processes, allowing air (low dielectric constant) to occupy spaces that would otherwise be filled with high-k insulating materials, thereby improving memory cell characteristics without adding complex external components
Solution Approach 2:
The patent implements three-dimensional stacked structures with multiple layers of lower and upper lines extending in different directions (first and second directions). By transitioning from planar to vertical stacking, the design achieves higher integration density while air gaps are strategically positioned in the third dimension (vertical spacing between stacked layers) to reduce electrical interference, thus solving both density and reliability requirements simultaneously
2Reliability
If air gaps are formed between upper lines to reduce capacitance, then read disturbance is prevented, but manufacturing process complexity increases
Solution Approach 1:
The patent forms sacrificial layers (such as mandrel structures or temporary fill materials) in the precise locations where air gaps are needed before forming the upper lines. These sacrificial layers are then selectively removed after the upper lines are formed, creating air gaps without requiring complex post-processing steps. This preliminary placement of sacrificial elements simplifies the overall process by integrating air gap formation into the existing fabrication sequence rather than adding separate air gap creation steps
Solution Approach 2:
The patent removes sacrificial layers or fill materials from specific regions to create air gaps between upper lines and between stacked structures. By extracting these temporary materials after they have served their structural purpose during fabrication, the design achieves reduced capacitance and improved memory characteristics without requiring direct air gap formation processes, thus maintaining manufacturing simplicity while achieving the desired electrical performance
3Productivity
If higher integration is achieved through stacked structures, then device density increases, but process difficulty and sheet resistance increase
Solution Approach 1:
The patent combines multiple functions into the stacked structure: lower and upper lines serve as both interconnects and as part of the memory cell structure, with memory cells formed at intersections. The same fabrication processes that create the stacked interconnect layers also form the memory cell structures, eliminating the need for separate processing steps for each component. This merging of functions achieves high integration density without proportionally increasing process complexity
Solution Approach 2:
The stacked structures with lower and upper lines extending in different directions serve multiple purposes: they provide electrical interconnects for memory cells, create capacitive coupling for memory operation, and define the physical structure for high-density integration. The air gaps between these structures simultaneously reduce parasitic effects and enable further density improvement. This multi-functionality allows a single structural element to address multiple design requirements, achieving high productivity without linearly increasing process complexity
Data Source
AI summary
An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.