Memory Device Air Gaps Reduce Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices, such as DRAM, are scaled down, the increased parasitic capacitance between adjacent memory cells limits operation speed due to reduced space between memory cells, leading to greater resistance-capacitance (RC) delay.
Innovation Solution
The introduction of air gaps between conductive pillars in the memory device, achieved by forming landing pads with a lower resistivity than the conductive pillars and recessing the sidewalls of the conductive pillars from the landing pads, reduces parasitic capacitance by using a dielectric material with a lower dielectric constant than solid dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to reduce device size, then device density is improved, but parasitic capacitance between adjacent memory cells increases
Solution Approach 1:
The patent extracts the harmful dielectric material from the spaces between adjacent conductive pillars and replaces it with air gaps. This is achieved by forming landing pads with recessed sidewalls that create void spaces, which are then filled with air instead of solid dielectric material, thereby removing the source of parasitic capacitance while maintaining the scaled-down device structure
Solution Approach 2:
The patent introduces porous air gap structures between adjacent conductive pillars. These air gaps are formed by creating recesses in the landing pads that extend into the dielectric layer, forming void spaces filled with air. The porous air gap structure reduces parasitic capacitance while allowing the device to maintain high density through continued scaling
2Quantity of substance
If space between adjacent memory cells is reduced to increase density, then device density is improved, but operation speed deteriorates due to increased RC delay
Solution Approach 1:
The patent removes solid dielectric material from the spaces between adjacent conductive pillars and replaces it with air gaps. This extraction of harmful material reduces parasitic capacitance and RC delay, thereby improving operation speed while maintaining the reduced cell spacing required for high device density
Solution Approach 2:
The patent changes the dielectric parameter of the material between conductive pillars from solid dielectric (high dielectric constant) to air (low dielectric constant). This parameter change reduces parasitic capacitance and RC delay, improving operation speed while allowing continued scaling for high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The formation of air gaps effectively lowers parasitic capacitance, thereby improving the operation speed of the memory device by reducing RC delay.
Implementation Method 1
parasitic capacitance between adjacent memory cells is increased
Implementation Method 2
reduces parasitic capacitance by using a dielectric material with a lower dielectric constant than solid dielectric materials
Data Source
AI summary
The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad.