Backend Memory Airgap Interconnects for Lower Parasitic Capacitance
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Solution Overview
Problem
As integrated circuits scale downward in size, densely packed interconnect structures face challenges with parasitic capacitance due to closely packed conductive structures like wordlines and bitlines, leading to degraded memory performance.
Innovation Solution
Incorporating airgaps between conductive features in interconnect layers, particularly between wordlines and bitlines, reduces parasitic capacitance by using low-k dielectric materials and inert gases, achieving a total k value below 2.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conductive structures are densely packed to increase integration density, then device area is reduced, but parasitic capacitance increases leading to degraded memory performance
Solution Approach 1:
The patent extracts the dielectric material between adjacent conductive structures and replaces it with airgaps. This removes the harmful parasitic capacitance-generating material while maintaining the dense packing of conductive structures, thereby reducing parasitic capacitance without increasing device area.
Solution Approach 2:
The patent introduces airgaps (porous spaces) between conductive structures in the interconnect layers. These airgaps have effectively k=0, creating a low-k environment that reduces parasitic capacitance between densely packed wordlines and bitlines while allowing tight pitch maintenance.
2Reliability
If airgaps are introduced between conductive structures to reduce parasitic capacitance, then memory performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming airgaps between conductive structures before completing the interconnect layer formation. This early creation of airgaps ensures low parasitic capacitance is achieved from the outset, and subsequent processing steps are designed to accommodate rather than create the airgaps, managing complexity proactively.
Solution Approach 2:
The patent uses airgaps as an intermediary medium between adjacent conductive structures. These airgaps serve as mediators that electrically isolate wordlines and bitlines, reducing parasitic capacitance coupling while allowing the conductive structures to remain in close proximity for high density.
3Area of stationary object
If tight pitch is achieved between memory cells to increase density, then area is reduced, but parasitic capacitance between interconnect structures increases
Solution Approach 1:
The patent applies local quality by introducing airgaps specifically in the interconnect layers where parasitic capacitance is most problematic, while maintaining dense packing elsewhere. The airgaps are strategically placed between wordlines and bitlines in regions where tight pitch is required, providing localized parasitic capacitance reduction without compromising overall memory cell density.
Solution Approach 2:
The patent creates a composite interconnect structure combining conductive materials (copper, cobalt, tungsten) with air (k=0 dielectric). This composite architecture allows tight pitch between memory cells while the air components provide electrical isolation, reducing parasitic capacitance between interconnect structures despite the dense packing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of airgaps between conductive layers in interconnect regions reduces parasitic capacitance, allowing for tighter pitches and lower energy consumption in memory cells, thereby enhancing memory performance.
Implementation Method 1
Structures formed in such interconnect layers may suffer from parasitic effects as they become more densely packed
Implementation Method 2
reduces parasitic capacitance by using low-k dielectric materials and inert gases, achieving a total k value below 2.0
Data Source
AI summary
Techniques are provided herein for forming backend memory structures with airgaps in an interconnect region above semiconductor devices. The airgaps may be provided between conductive features, such as wordlines, to reduce parasitic capacitance. An interconnect region above a plurality of semiconductor devices includes any number of interconnect layers. A first interconnect layer includes first conductive layers (e.g., wordlines) extending in a first direction with airgaps between adjacent first conductive layers. A second interconnect layer over the first interconnect layer includes at least portions of memory cells over corresponding first conductive layers. A third interconnect layer over the second interconnect layer includes a second conductive layer (e.g., bitline) extending in a second direction over one or more of the at least portions of memory cells. The presence of airgaps between the first conductive layers allows for a tighter pitch between memory cells and reduced total energy consumption among the memory cells.