Stacked Memory Alignment Keys and TSVs for Stress Reduction
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Solution Overview
Problem
During the stacking of semiconductor memory devices, mechanical stress causes chips to arc or tilt due to inadequate alignment and support, leading to reduced structural integrity and potential malfunction as the number of chips increases.
Innovation Solution
The use of through-silicon vias (TSVs) to form alignment patterns and keys at the corners of the chips, which provide both structural support and precise alignment, reducing mechanical stress and improving electrical characteristics by acting as both alignment keys and power TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stacking methods are used with TSVs only in central regions, then electrical coupling is achieved, but mechanical stress causes chips to arc or tilt due to inadequate alignment and support
Solution Approach 1:
The patent divides the TSV distribution into two functional segments: central TSVs for electrical coupling and corner alignment keys with TSVs for mechanical support and alignment. This segmentation allows each region to perform its specialized function, preventing chip arcing and tilting while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from a single central TSV arrangement to a two-dimensional distribution pattern incorporating both central TSVs and corner alignment keys. This dimensional expansion provides distributed mechanical support across the chip surface, preventing stress-induced deformation.
2Quantity of substance
If the number of stacked chips is increased to enhance memory capacity, then memory capacity increases, but mechanical stress and misalignment phenomena become more severe
Solution Approach 1:
The corner alignment keys with integrated TSVs perform preliminary alignment and mechanical stabilization during the stacking process. This preliminary action ensures that subsequent chips in the stack can be accurately positioned, maintaining alignment precision even as the number of stacked chips increases.
Solution Approach 2:
The alignment keys positioned at the corners provide beforehand cushioning against mechanical stress by distributing loads across multiple support points. This prevents stress concentration that would otherwise lead to chip arcing and tilting in multi-chip stacks.
3Measurement precision
If alignment patterns are formed at corners of chips, then alignment accuracy is improved, but additional TSVs are required increasing device complexity
Solution Approach 1:
The patent merges the alignment pattern function and electrical coupling function into a single integrated structure. The corner alignment keys contain TSVs that simultaneously provide mechanical alignment references and electrical connections, eliminating the need for separate alignment features and reducing overall device complexity.
Solution Approach 2:
The corner alignment keys serve multiple functions: they provide mechanical support, enable precise alignment, and establish electrical connections. This multi-functionality reduces the total number of separate structures needed, simplifying the overall device design despite the increased alignment requirements.
Data Source
AI summary
A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions.