Memory Allocation in Multi-Core Systems via Distance-Based Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-core systems, memory allocation to processing cores is inefficient, leading to irregular access times and making it difficult to estimate execution times for tasks, especially when task migration occurs or errors arise, resulting in performance deterioration and incorrect scheduling.
Innovation Solution
A memory management method that uses a hierarchical structure to allocate memories based on distances from processing cores, employing a memory controller, bridge or router, scheduler, and address translation unit to set memory allocation orders and maintain consistent access times through task migration and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memories are allocated to processing cores in a multi-core system, then the system can perform parallel tasks, but memory allocation becomes inefficient and access times become irregular
Solution Approach 1:
The patent segments the memory space into multiple regions, with each region assigned to a specific processing core. This segmentation ensures that each core has dedicated memory access paths, eliminating contention and irregular access times while maintaining parallel execution capability. The memory management unit translates logical addresses to physical addresses based on the core-memory region mapping.
Solution Approach 2:
The patent introduces a memory management unit (MMU) as an intermediary between processing cores and the physical memory system. The MMU handles address translation and memory allocation decisions, ensuring that each core accesses its allocated memory region efficiently. This intermediary layer abstracts the complexity of memory management from the cores while maintaining regular access patterns.
2Adaptability or versatility
If task migration is implemented in multi-core systems, then system flexibility improves, but execution time estimation becomes inaccurate due to irregular memory access times
Solution Approach 1:
The patent performs preliminary memory allocation and address space setup during task scheduling, before task migration occurs. The memory management unit pre-configures the address translation tables and memory region mappings for potential task migrations. This preliminary action ensures that when task migration happens, the memory access patterns remain regular and predictable, allowing accurate execution time estimation.
3Productivity
If more processing cores are added to improve performance, then parallel processing capability increases, but memory management complexity and access time irregularity worsen
Solution Approach 1:
The patent divides the memory system into segmented regions, with each region dedicated to specific processing cores. This segmentation scales efficiently with the number of cores, as each core receives its own memory region without increasing overall system complexity. The memory management unit uses a systematic addressing scheme that automatically adapts to the number of cores.
Solution Approach 2:
The memory management unit is designed as a universal component that handles memory allocation and address translation for all processing cores using the same methodology. This multi-functional approach allows the system to scale to any number of cores without requiring core-specific memory management logic, thereby controlling complexity while maintaining parallel processing capability.
Data Source
AI summary
A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a task to be performed by a processing core and it is possible to secure the same memory access time when a task is migrated between processing cores by setting a memory allocation order according to distances from the processing cores to the memories in correspondence with the processing cores, translating a logical address to be processed by one of the processing cores according to the set memory allocation order into a physical address of one of the memories, and allocating a memory corresponding to the translated physical address to the processing core.