Memory Address Allocation Tree for Variable-Size Data

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Solution Overview

Problem

Existing memory management techniques for neural network accelerators result in low space utilization and storage space fragmentation due to the inability to efficiently allocate storage space for variable-sized data, leading to inefficiencies in computation and power consumption.

Innovation Solution

A method involving the formation of a tree structure with memory blocks having total and available storage size identifiers, where each block is used as a node to allocate storage space based on the size of the data, allowing for efficient allocation and utilization of storage space even for data with unknown sizes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional memory allocation methods (best fit, graph coloring) are used, then allocation speed is improved, but space utilization deteriorates due to fragmentation

Engineering Contradiction:
Improveallocation speedVSAvoidspace utilization
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The memory space is segmented into multiple memory blocks, each with a specific size. This segmentation allows the system to allocate precise blocks to data of variable sizes, reducing internal fragmentation while maintaining efficient allocation. The memory blocks are organized in a tree structure that enables both fast searching and optimal matching.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the parameter of memory allocation from fixed-size registers to variable-size memory blocks. By dynamically adjusting the size of allocated memory blocks to match the actual data size, the system achieves both high allocation speed and high space utilization, eliminating the traditional trade-off between these two parameters.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If fixed-length registers are used for allocation, then allocation simplicity is improved, but adaptability deteriorates for variable-sized data

Engineering Contradiction:
Improveallocation simplicityVSAvoidadaptability to variable-sized data
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The invention introduces dynamic memory block sizes that can adapt to different data requirements. The tree structure of memory blocks allows the system to dynamically select and allocate blocks of appropriate sizes for variable-sized data, maintaining allocation simplicity while achieving high adaptability. Each memory block's size is determined based on the actual data size, enabling flexible resource allocation.

Inventive Principle:
Principle #15Dynamics

3Productivity

If immediate number-based space assignment is used, then allocation speed is improved, but space utilization deteriorates due to insufficient optimization

Engineering Contradiction:
Improveallocation speedVSAvoidspace utilization
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The invention introduces a tree structure of memory blocks as an intermediary between the allocation request and the physical memory space. This intermediary structure enables both fast allocation (by providing a organized framework for quick searching) and optimal space utilization (by allowing precise matching of data size to block size). The tree structure acts as a mediator that reconciles the conflict between speed and optimization.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4155946B1Method and device for allocating storage addresses for data in memory
Publication Date: 2026.02.25 CAMBRICON (XIAN) SEMICON CO LTD
  • EP4155946B1 patent drawingFigure 1a~1c
  • EP4155946B1 patent drawingFigure 1d~2a
  • EP4155946B1 patent drawingFigure 2b~3

AI summary

The present disclosure relates to a method, a device and a computation apparatus for allocating a space address to data in a memory, where the computation apparatus is included in a combined processing apparatus, which includes a general interconnection interface and other processing apparatuses. The computation apparatus interacts with other processing apparatuses to jointly complete computations specified by the user. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and the other processing apparatuses, and is used for storing data of the computation apparatus and other processing apparatuses. The technical solutions of the present disclosure improve utilization of storage space of the memory.