Memory Allocator Single Atomic Operation Concurrency

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Solution Overview

Problem

Existing memory allocation techniques in multi-processor environments face challenges with concurrency, leading to increased time and performance overhead due to the need for multiple atomic operations, which can impair efficiency and fragment memory.

Innovation Solution

A memory allocator performs memory allocation in a single atomic operation by reading, checking, and updating a data structure to allocate memory, ensuring atomicity and preventing concurrent access issues, while also releasing memory and reusing freed regions efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple atomic operations are used for memory allocation in multi-processor environments, then concurrency is addressed, but time overhead and performance are increased

Engineering Contradiction:
Improveconcurrency handlingVSAvoidmemory allocation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines multiple atomic operations (reading allocation state, checking availability, updating allocation state, and returning address) into a single atomic operation. This is achieved by implementing a memory allocator that performs all these steps atomically in one hardware-supported atomic instruction, eliminating the need for multiple separate atomic operations and their associated synchronization overhead.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the memory pool into multiple independent regions, each with its own allocation state stored in a data structure. This segmentation allows the atomic operation to work on smaller, manageable units of memory, improving cache performance and reducing the complexity of the atomic operation while maintaining concurrency safety.

Inventive Principle:
Principle #1Segmentation

2Reliability

If multiple atomic operations are performed for memory allocation, then proper synchronization is achieved, but performance overhead increases

Engineering Contradiction:
ImprovesynchronizationVSAvoidallocation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the read-check-update-return sequence into a single atomic operation, eliminating multiple synchronization points. This single atomic operation maintains proper synchronization and memory visibility across processors while removing the performance penalty of multiple atomic instructions and their associated memory barriers.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If standard atomic operations are used for memory allocation, then concurrency is handled, but memory fragmentation increases

Engineering Contradiction:
Improveconcurrency controlVSAvoidmemory fragmentation
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent divides the memory pool into segmented regions and maintains a data structure that tracks allocation state for each region. This segmentation enables more efficient packing of allocations and reduces external fragmentation by allowing the allocator to manage memory in organized units rather than as a single contiguous block.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240054016A1Accelerated memory allocation
Publication Date: 2024.02.15 NEXTSILICON LTD
  • US20240054016A1 patent drawing
  • US20240054016A1 patent drawing
  • US20240054016A1 patent drawing

AI summary

There is provided a device for allocation of memory configured for: in response to a request for allocation of a region of a pool of a memory by a process being executed by a processor, a memory allocator is configured to perform in a single atomic operation: read a data structure indicating a state of allocation of the pool, check the data structure for a condition, update the data structure according to an outcome of the check, and return an address of the allocated region of the memory.