Memory Device Analog Digital I/O Interface Multi-Level Read

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Solution Overview

Problem

Traditional solid-state memory devices face inefficiencies in programming and reading operations due to their binary nature, which becomes cumbersome as more bits are stored per cell, leading to longer operation times and increased complexity.

Innovation Solution

The memory devices utilize threshold voltage ranges to represent multiple data values, allowing for single operations to program and read complete bit patterns instead of discrete bits, and employ analog voltage signals to simplify data handling through sample and hold circuitry and analog-to-digital conversion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If binary read/write operations are used in traditional solid-state memory devices, then data can be stored and retrieved, but operation times increase and efficiency decreases as more bits are stored per cell

Engineering Contradiction:
Improveoperation speedVSAvoidoperation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent changes the fundamental parameter of data representation from binary (0 or 1) to multi-level threshold voltage ranges. Each memory cell stores data as a specific threshold voltage within a defined range, allowing a single read operation to retrieve multiple bits of information simultaneously. This parameter change directly addresses the contradiction by enabling faster operations without increasing operation time, as the memory device can read entire multi-bit values in one operation rather than requiring multiple sequential binary operations.

Inventive Principle:
Principle #35Parameter changes

2Loss of information

If multiple binary operations are performed to read multi-bit data, then complete data patterns can be retrieved, but the complexity of data handling increases

Engineering Contradiction:
Improvedata retrieval completenessVSAvoiddata handling complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent merges multiple binary read operations into a single multi-level read operation. By combining the retrieval of multiple bits that were previously accessed sequentially into one simultaneous operation, the system reduces data handling complexity while ensuring complete data pattern retrieval. The memory controller reads the threshold voltage range directly, obtaining all stored bits in a single operation rather than requiring multiple separate binary reads.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory device achieves multi-functionality by using a single read operation to perform what previously required multiple specialized binary operations. The threshold voltage range reading mechanism universally handles retrieval of any multi-bit pattern stored in the cell, eliminating the need for separate operations for different data patterns and reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If threshold voltage ranges are used to represent multiple data values, then storage density increases and operation efficiency improves, but the interface complexity between digital controllers and analog memory cells increases

Engineering Contradiction:
Improvestorage densityVSAvoidinterface complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary sensing mechanism that bridges the digital controller and analog memory cells. The sense amplifier reads the threshold voltage range of memory cells and converts this analog information into digital signals that the controller can process. This intermediary layer handles the complexity of analog-to-digital conversion, allowing the digital controller to interact with memory cells using simplified digital read/write commands while the intermediary manages the threshold voltage range interpretation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8526243B2Configurable digital and analog input/output interface in a memory device
Publication Date: 2013.09.03 MICRON TECHNOLOGY INC
  • US8526243B2 patent drawing
  • US8526243B2 patent drawing
  • US8526243B2 patent drawing

AI summary

Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.