Memory Device Analog Voltage Storage

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Solution Overview

Problem

Traditional solid-state memory devices face inefficiencies in data storage and retrieval due to the need for multiple program and read operations as bit counts increase, leading to longer operation times and higher power consumption, while also having lower storage capacities compared to HDDs.

Innovation Solution

The implementation of a memory device that stores data as threshold voltage ranges, allowing for single operations to represent complete bit patterns rather than discrete bits, using sample and hold circuitry to manage analog voltage signals and reduce the number of read/write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional solid-state memory devices store data as discrete bits requiring multiple program and read operations, then data storage and retrieval can be performed reliably, but operation time increases and power consumption increases as bit counts increase

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines multiple discrete bit operations into a single analog voltage operation. Instead of performing separate program and read operations for each bit, the system uses analog voltage levels to represent multiple bits simultaneously, merging multiple operations into one unified analog operation that reduces total operation time while maintaining data reliability through the analog representation method

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the fundamental parameter representation from discrete digital bits to continuous analog voltage levels. By storing data as analog voltage values rather than discrete binary states, the system enables single operations to represent complete bit patterns, significantly reducing the number of operations required and thereby decreasing operation time while preserving data integrity through the analog storage mechanism

Inventive Principle:
Principle #35Parameter changes

2Reliability

If traditional solid-state memory devices store data as discrete bits requiring multiple program and read operations, then data can be stored with current technology, but power consumption increases as bit counts increase

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges multiple discrete bit operations into a single analog operation, reducing the total number of program and read cycles required. Since each discrete operation consumes power, consolidating multiple bit operations into one analog operation directly reduces overall power consumption while maintaining the reliability of data storage through the analog representation method

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

By changing from discrete digital bit storage to continuous analog voltage storage, the system reduces the number of sequential operations needed. This parameter change eliminates the need for multiple powered operations per data element, thereby reducing total power consumption while preserving data reliability through the analog storage mechanism that can represent multiple bits in a single voltage state

Inventive Principle:
Principle #35Parameter changes

3Reliability

If solid state drives use semiconductor memory devices, then operation is not subject to vibration, shock or magnetic field concerns and power requirements are lower, but storage capacities are much lower compared to HDDs

Engineering Contradiction:
Improveoperational reliabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent changes the data representation parameter from discrete digital bits to continuous analog voltage levels, enabling each memory cell to store multiple bits simultaneously. This parameter change effectively multiplies the storage capacity of each memory device without changing the physical hardware, allowing SSDs to achieve HDD-level capacities while maintaining their operational reliability advantages against vibration, shock, and magnetic fields

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent adds an analog voltage dimension to traditional digital memory storage. By utilizing the continuous voltage range rather than just discrete high/low states, the system creates an additional dimension of data representation that exponentially increases storage capacity per memory cell, enabling SSDs to match or exceed HDD capacities while preserving their solid-state reliability benefits

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces operation time and power consumption by enabling a single read or write operation to represent multiple bits, enhancing storage capacity and efficiency compared to traditional devices.

Implementation Method 1

stores data as threshold voltage ranges, allowing for single operations to represent complete bit patterns

Methodology Applied
Scientific EffectThreshold voltage storage:

Implementation Method 2

using sample and hold circuitry to manage analog voltage signals and reduce the number of read/write operations

Methodology Applied
Scientific EffectSample and hold:

Data Source

PatentUS8560766B2Non-volatile memory device having assignable network identification
Publication Date: 2013.10.15 MICRON TECHNOLOGY INC
  • US8560766B2 patent drawing
  • US8560766B2 patent drawing
  • US8560766B2 patent drawing

AI summary

Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.