Memory Arbiter Latency Guarantee for Multi-Port SoC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Systems-on-chip (SoCs) face challenges in managing memory access latency for multiple clients with varying real-time constraints, as existing technologies struggle to ensure that clients with hard deadlines meet their latency requirements while accommodating those with softer deadlines.
Innovation Solution
A memory controller with a memory arbiter that determines priorities based on latency measurements, using latency determiners to calculate delta priority values from target latency values, ensuring that clients with recent latency deviations receive higher priority, thus guaranteeing average latency for selected ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory access is prioritized for clients with hard deadlines, then latency requirements for real-time processes are met, but memory access for other clients may be delayed
Solution Approach 1:
The memory arbiter dynamically adjusts priority values for different ports based on their latency performance history. Ports that have experienced latency deviations above their target values receive increased priority, while ports performing well maintain or reduce priority. This dynamic adjustment allows the system to guarantee latency for real-time clients when needed while fairly serving other clients under normal conditions.
Solution Approach 2:
The system implements feedback through latency determiners that continuously monitor actual latency values and compare them against target latency values for each port. This feedback loop enables the arbiter to make informed priority adjustments, ensuring that ports experiencing latency violations receive compensatory priority boosts in subsequent access cycles.
2Device complexity
If a single memory controller serves all clients, then device complexity is reduced, but it becomes difficult to meet diverse latency requirements of different clients
Solution Approach 1:
The memory controller is segmented into multiple independent ports, each associated with specific clients and having its own latency determiner and priority value. This segmentation allows each port to be independently managed and optimized for its specific client's latency requirements, while still operating under a unified arbiter that coordinates access to the shared memory resource.
Solution Approach 2:
The single memory controller is designed to serve multiple clients with different latency requirements through multiple ports. The universal arbiter manages all ports and can adapt its priority allocation based on real-time latency performance, enabling one controller to handle diverse client needs without requiring separate dedicated controllers for each client type.
3Productivity
If memory access latency is minimized for all clients, then overall SoC performance increases, but it becomes difficult to guarantee average latency bounds for specific client sets
Solution Approach 1:
The system applies different quality of service characteristics to different ports. Each port has its own target latency value and priority value, allowing the arbiter to optimize memory access for specific ports that require guaranteed average latency bounds while allowing other ports more flexibility. This local differentiation enables the system to maintain high overall performance while ensuring reliability for critical clients.
Data Source
AI summary
Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.