Multi-Stage Memory Controller Arbiter for High-Speed Scheduling
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Solution Overview
Problem
Memory controllers face challenges in operating at fast enough speeds to efficiently schedule memory accesses in modern high-speed memory systems, particularly with deep queues and modern memory technologies like DDR4, where scanning and picking accesses while utilizing available bus bandwidth becomes difficult.
Innovation Solution
A memory controller architecture that includes a command queue and an arbiter with multiple sub-arbiters to select memory commands, allowing for efficient arbitration and scheduling of memory access requests, including page hits, conflicts, and misses, to optimize memory bus usage and reduce overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single arbitration stage is used in the memory controller, then the device complexity is reduced, but the productivity decreases due to inability to efficiently schedule deep queues at high speeds
Solution Approach 1:
The arbiter is divided into multiple arbitration stages (first arbitration stage, second arbitration stage, etc.) that process memory access requests in sequence. Each stage handles a portion of the arbitration logic, allowing the system to efficiently schedule deep queues at high speeds while distributing the computational complexity across multiple manageable components rather than requiring a single complex arbitration unit
2Productivity
If the memory controller operates at higher clock frequencies to match DDR4 speeds, then the productivity increases, but the device complexity increases due to the difficulty of operating scheduling logic at such speeds
Solution Approach 1:
The arbitration process is segmented into multiple stages that can operate at different effective speeds. The multi-stage arbitration allows the controller to process scheduling decisions through a pipeline that can be synchronized with DDR4 clock frequencies, breaking down the complex timing requirements into manageable stages that are easier to implement and maintain at high speeds
Solution Approach 2:
The first arbitration stage performs preliminary arbitration on incoming memory access requests before they reach the second arbitration stage. This preliminary processing prepares the requests in advance, reducing the timing pressure on subsequent stages and allowing the overall system to operate at high DDR4 speeds without requiring every component to operate at maximum frequency simultaneously
Data Source
AI summary
In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.