Memory Subsystem Arbitration Circuitry for VM Resource Management

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Solution Overview

Problem

Conventional hypervisor-based memory sub-systems are inefficient in enforcing service-level agreements (SLAs) for virtual machines (VMs), leading to resource starvation and bottlenecks, which can violate SLAs and limit system efficiency.

Innovation Solution

Implementing arbitration circuitry within the memory sub-system to directly manage I/O traffic from VMs, using Single-Root I/O Virtualization (SRIOV) and PCIe functions, allowing native access while enforcing SLAs, thereby balancing resource allocation and ensuring compliance with quality of service (QOS) thresholds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a hypervisor is used to manage I/O traffic from VMs to memory sub-system, then resource allocation flexibility is improved, but system efficiency and SLA enforcement capability deteriorate due to software-based overhead and resource starvation issues

Engineering Contradiction:
Improveresource allocation flexibilityVSAvoidsystem efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces arbitration circuitry as a hardware intermediary between VMs and the memory sub-system. This circuitry receives I/O traffic from multiple VMs, enforces SLA-based policies, and manages resource allocation without requiring software hypervisor intervention for each operation. The arbitration circuitry acts as a dedicated hardware mediator that balances flexibility with efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the software-based hypervisor control mechanism with a hardware-based arbitration circuitry. By implementing SLA enforcement and resource allocation logic in hardware (circuitry) rather than software (hypervisor), the system eliminates software overhead and achieves near-native access performance while maintaining policy enforcement capabilities.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of operation

If hypervisor-based management is used, then ease of operation is improved, but SLA compliance and resource protection deteriorate due to resource starvation and bottlenecks

Engineering Contradiction:
Improveease of operationVSAvoidSLA compliance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The arbitration circuitry is pre-configured with SLA policies and quality of service thresholds before operation. These policies are programmed into the hardware circuitry in advance, enabling automatic enforcement without real-time software intervention. This preliminary configuration ensures consistent SLA compliance while maintaining operational simplicity.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If native access is enabled for VMs to memory sub-system, then system efficiency is improved, but resource overutilization and SLA violation risks increase

Engineering Contradiction:
Improvesystem efficiencyVSAvoidresource overutilization risk
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The arbitration circuitry continuously monitors resource usage by each VM and compares it against configured quality of service thresholds. When a VM approaches or exceeds its allocated resources, the circuitry automatically enforces rate limiting or blocking to prevent overutilization. This real-time feedback mechanism maintains near-native access performance while preventing SLA violations.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11836511B2Function arbitration and quality of service for memory commands
Publication Date: 2023.12.05 MICRON TECHNOLOGY INC
  • US11836511B2 patent drawing
  • US11836511B2 patent drawing
  • US11836511B2 patent drawing

AI summary

A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.