Memory Arbitration for Image Forming Apparatuses
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Solution Overview
Problem
Image forming apparatuses face challenges in efficiently managing high-speed memory operations due to differing latency requirements for reading and writing, leading to inefficiencies and potential data loss or omission, particularly in handling large-capacity DDR memory.
Innovation Solution
A memory control method that employs an arbitration system to prioritize transactions based on burst numbers and Quality of Service (QOS) values, using a DCV value to manage latency and ensure efficient processing by switching between write and read operations dynamically, thereby preventing data disposal or omission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory control apparatus processes read and write operations simultaneously without arbitration, then the memory bandwidth utilization is improved, but data loss or omission occurs due to conflicting latency requirements
Solution Approach 1:
The arbitration system dynamically adjusts priority levels for read and write operations based on real-time conditions. The priority inversion mechanism allows the system to switch between read-priority and write-priority modes, enabling flexible adaptation to different operational scenarios while maintaining both high bandwidth utilization and data integrity
Solution Approach 2:
The system employs feedback mechanisms where the arbitration queue monitors the state of read and write operations, and adjusts priority assignments accordingly. This closed-loop control ensures that data integrity is maintained while optimizing memory bandwidth utilization through adaptive priority management
2Reliability
If the system prioritizes read operations to meet latency requirements, then read operation reliability is improved, but write operations may experience data loss
Solution Approach 1:
The system takes preliminary anti-action by implementing a priority inversion mechanism that proactively prevents write data loss. When write operations are detected to be at risk, the system preemptively elevates their priority, counteracting the potential harmful effect of read-priority scheduling before data loss can occur
Solution Approach 2:
The arbitration system changes the priority parameter dynamically based on operational conditions. By adjusting the priority level parameter for read and write operations, the system can shift between read-optimized and write-optimized modes, preventing data loss while maintaining read operation reliability
3Loss of information
If the system prioritizes write operations to prevent data loss, then write data integrity is improved, but read operations may experience increased latency
Solution Approach 1:
The system dynamically adjusts write operation priority based on the state of the arbitration queue and current operational needs. This dynamic priority adjustment ensures write data integrity is maintained while minimizing the impact on read operation latency through adaptive scheduling
Solution Approach 2:
The arbitration system implements periodic evaluation of operation priorities, allowing it to switch between write-priority and read-priority modes. This periodic reassessment ensures that write data integrity is maintained while preventing excessive read latency through timely priority switches
4Device complexity
If the memory control apparatus uses a simple FIFO arbitration queue, then device complexity is reduced, but efficiency deteriorates due to inability to handle differing latency requirements
Solution Approach 1:
The arbitration queue implements dynamic priority assignment rather than static FIFO ordering. This allows the system to maintain a relatively simple queue structure while achieving high operational efficiency through flexible, condition-based priority management that adapts to different latency requirements
Solution Approach 2:
The system changes the priority parameter of operations in the arbitration queue based on their type and current system state. This parameter modification enables efficient handling of mixed read/write operations without requiring a complex multi-queue structure, maintaining simplicity while improving productivity
Data Source
AI summary
A memory control method includes: attaching transfer IDs to generate write control data and attaching transfer IDs to generate read control data for respective predetermined areas; executing an arbitration that determines a priority order of processing taking the write control data and the read control data that are stored in an arbitration queue as targets; and adding a burst number of a Read command or a Write command to complete a transaction in response to an execution of an Activate command to execute the transaction while decrementing a burst number in response to an execution of the Read command or the Write command, so as to update a remaining burst number as a remaining number of bursts. The arbitration raises a priority order of the Activate command to execute a transaction having a large burst number when the remaining burst number is less than a preliminarily set threshold.