Hierarchical Memory Arbitration for Network Device Load Balancing
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Solution Overview
Problem
Existing memory systems in network devices face challenges in efficiently managing memory access across multiple ports and switching cores, leading to inefficiencies in data processing and transmission due to the lack of effective load balancing and hierarchical memory organization.
Innovation Solution
A circuit and method that utilize a hierarchical memory structure with multiple memory banks, where a first-level memory bank is composed of smaller second-level memory banks, and include arbitration circuitry to control multiplexing paths, allowing simultaneous memory access from different memory access circuits to different second-level memory banks within the same first-level memory bank, segmenting requests into sub-requests, and buffering them for efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory is shared among multiple memory access sources in network devices, then memory resource utilization is improved, but memory access efficiency deteriorates due to lack of load balancing
Solution Approach 1:
The memory system is segmented into multiple independent memory banks (first memory bank, second memory bank, third memory bank, fourth memory bank) that can be accessed simultaneously. Each memory bank operates independently, allowing parallel memory access operations across different memory access sources, thereby improving both resource utilization and access efficiency.
2Productivity
If hierarchical memory organization is implemented, then memory access parallelism is improved, but system complexity increases
Solution Approach 1:
The patent introduces a hierarchical dimension to the memory organization, with first-level memory banks (first and second memory banks) and second-level memory banks (third and fourth memory banks). This hierarchical structure enables parallelism at multiple levels simultaneously, achieving high memory access parallelism while managing complexity through structured organization.
Solution Approach 2:
The hierarchical memory structure implements a nested organization where third and fourth memory banks are nested within the first and second memory banks respectively. This nesting allows for efficient memory access control and management while enabling parallel operations across different hierarchical levels.
3Speed
If multiple memory access circuits access memory simultaneously, then data processing speed is improved, but access conflicts increase
Solution Approach 1:
The memory system is divided into multiple independent memory banks that can be accessed simultaneously without interfering with each other. Multiple memory access circuits can access different memory banks in parallel, achieving high data processing speed while avoiding access conflicts through spatial separation of memory resources.
Solution Approach 2:
The system performs preliminary segmentation of memory access requests into different memory banks before actual access occurs. This preliminary routing ensures that simultaneous access requests are directed to different memory banks, preventing conflicts before they arise and maintaining high processing speed.
Data Source
AI summary
Aspects of the disclosure provide a circuit that includes a plurality of memory access circuits configured to access a memory to read or write data of a first width. The memory includes a plurality of memory banks that are organized in hierarchy. Further, the circuit includes a plurality of interface circuits respectively associated with the plurality of memory access circuits. Each interface circuit is configured to receive memory access requests to first level memory banks from an associated memory access circuit, segment the memory access requests into sub-requests to corresponding second level memory banks, buffer the sub-requests into buffers associated with the second level memory banks. In addition, the circuit includes arbitration circuitry configured to control multiplexing paths from the buffers to the second level memory banks to enable, in a same memory access clock, memory accesses by the memory access circuits.