Semiconductor Memory Arbitration Circuit for Refresh Timing
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Solution Overview
Problem
Mounting multiple memory chips in one package does not ensure sufficient operational reliability due to the risk of overlapping refresh operations, which can lead to peak currents that may cause power capacity issues and interfere with micro-signals, potentially resulting in erroneous operations.
Innovation Solution
A semiconductor memory device with multiple memory blocks, each having an arbitration circuit that delays the start of commands to prevent overlapping refresh operations, ensuring that peak currents do not interfere with micro-signals and maintaining operational reliability without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple memory chips are mounted in one package to realize high integration and downsizing, then device integration and size reduction are improved, but operational reliability deteriorates due to overlapping refresh operations causing peak currents
Solution Approach 1:
The arbitration circuit performs preliminary action by detecting command overlaps between multiple memory channels before they execute, and generating delay signals in advance to prevent simultaneous refresh operations. This preliminary detection and signal generation eliminates the risk of peak current interference while maintaining the integrated compact structure.
Solution Approach 2:
The arbitration circuit acts as an intermediary between the command generating circuits of different memory channels and the memory cores. It receives commands from multiple channels, detects overlaps, generates appropriate delay signals, and coordinates execution timing, thereby enabling reliable operation of integrated multiple memory chips without direct conflicts.
2Productivity
If refresh operations are performed simultaneously in multiple channels to improve productivity, then data refresh efficiency is improved, but peak currents interfere with micro-signals causing erroneous operations
Solution Approach 1:
The arbitration circuit performs preliminary detection of command overlaps and generates delay signals before simultaneous refresh operations occur. This preliminary action prevents peak current interference with micro-signals while maintaining efficient parallel refresh operations across multiple channels when safe to do so.
Solution Approach 2:
The system dynamically adjusts refresh operation timing based on real-time command overlap detection. The arbitration circuit generates delay signals only when necessary to prevent interference, allowing dynamic optimization of refresh efficiency while eliminating harmful peak current effects on micro-signals.
3Reliability
If command execution is delayed to prevent overlapping refresh operations and ensure reliability, then operational reliability is improved, but command execution time increases
Solution Approach 1:
The arbitration circuit dynamically generates delay signals only when command overlaps are detected, rather than implementing fixed delays. This dynamic approach ensures reliability by preventing peak current interference only when necessary, while minimizing command execution time delays in non-overlapping scenarios.
Solution Approach 2:
The system changes the timing parameter of command execution dynamically based on detected overlaps. When overlaps occur, the arbitration circuit adjusts execution timing by generating delay signals; when no overlaps exist, commands execute immediately. This parameter adjustment optimizes both reliability and execution time.
Data Source
AI summary
A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped.