Memory Array Access Circuits for Reducing Standby Current
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Solution Overview
Problem
Semiconductor devices, such as DRAM, face challenges in reducing standby power consumption due to leakage and parasitic currents, which are influenced by standby voltage conditions, and existing solutions do not effectively accommodate various system voltages to minimize standby current consumption.
Innovation Solution
The semiconductor device employs a configuration with a memory array and access circuits that include activation voltage circuits and sense amplifiers, which provide optimized voltage levels for standby mode to reduce current consumption, using precharge voltages and control signals to manage the activation and read/write operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is provided to memory circuits to maintain standby voltage conditions, then data states are maintained during standby, but standby current consumption increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the standby voltage level provided to memory circuits based on the system voltage. When system voltage is high, a higher standby voltage is provided to maintain data states with lower leakage current. When system voltage is low, a lower standby voltage is provided. This adaptive voltage adjustment resolves the contradiction by optimizing both data state maintenance and standby current consumption based on actual operating conditions.
2Loss of energy
If standby voltage conditions are optimized to reduce leakage current, then standby current consumption decreases, but the ability to accommodate various system voltages is reduced
Solution Approach 1:
The patent implements dynamics by making the standby voltage provision adaptive and dynamic rather than fixed. The voltage level provided to memory circuits during standby is dynamically adjusted based on the detected system voltage level. This dynamic adaptation allows the system to accommodate various system voltages while simultaneously optimizing standby current consumption for each specific voltage condition.
3Reliability
If refresh operations are performed during standby to maintain data states, then data reliability is maintained, but power consumption during standby increases
Solution Approach 1:
The patent applies parameter changes by adjusting the voltage level during standby operations to reduce refresh power consumption. By providing an optimized standby voltage that is appropriate for the system voltage level, the refresh operations consume less power while still effectively maintaining data states. This resolves the contradiction between data reliability and standby power consumption.
Data Source
AI summary
Apparatuses and methods for reducing standby current in memory array access circuits are disclosed. An example apparatus includes a activation voltage supply line and a sense amplifier coupled to the activation voltage supply line. The sense amplifier is configured to be activated by an activation voltage provided on the activation voltage supply line. A read-write circuit is coupled to a pair of local input/output lines and a pair of global input/output lines, and further coupled to the activation voltage supply line. The read-write circuit is configured to drive the pair global input/output lines based on voltages of the pair of local input/output lines when activated for a read operation and further configured to drive the pair of local input/output lines based on voltages of the pair of global input/output lines when activated for a write operation.