Memory Array Access Line Resistance Measurement

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Solution Overview

Problem

Variabilities in the fabrication of memory devices lead to inconsistencies in operational parameters such as voltage levels and timing characteristics across different memory components, making it challenging to determine accurate baseline operating characteristics for flash memory arrays like NAND flash memory.

Innovation Solution

A method is introduced to measure the resistive characteristics of access lines by forming current paths through them, allowing for the determination of resistance values which can be used to adjust operational parameters for similar access lines, thereby improving the accuracy of memory operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional fabrication processes are used for memory devices, then manufacturing complexity is reduced, but operational parameter consistency deteriorates due to fabrication variabilities

Engineering Contradiction:
Improveoperational parameter consistencyVSAvoidmeasurement and adjustment system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing resistance measurements and operational parameter adjustments during the fabrication process itself, before the memory devices are fully assembled and deployed. This allows baseline operating characteristics to be determined early, enabling compensatory measures to be built into the device structure during manufacturing, thereby improving operational consistency without requiring complex post-fabrication adjustment systems.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using measured resistance values of access lines to dynamically adjust operational parameters such as voltage levels and timing characteristics. The system continuously monitors actual performance deviations from expected baseline characteristics and applies corrective adjustments to compensation structures, creating a closed-loop control system that maintains operational parameter consistency despite fabrication variabilities.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If fabrication variabilities are not accounted for, then manufacturing process is simpler, but operational accuracy deteriorates

Engineering Contradiction:
Improveoperational parameter determination accuracyVSAvoidmanufacturing process complexity
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent performs resistance measurements and establishes baseline operating characteristics during the fabrication process itself, before devices are fully assembled. This preliminary characterization allows accurate determination of operational parameters to be built into the device structure during manufacturing, improving measurement precision without requiring complex post-fabrication adjustment systems.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables memory devices to self-characterize their own operational parameters through integrated measurement structures that are part of the normal device architecture. The devices perform self-testing and self-adjustment using their own internal resources, eliminating the need for external measurement equipment and complex manufacturing processes while achieving high operational parameter determination accuracy.

Inventive Principle:
Principle #25Self-service

3Reliability

If baseline operating characteristics are not determined, then device operation is simpler, but performance consistency deteriorates

Engineering Contradiction:
Improvememory operation consistencyVSAvoidtesting and adjustment system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent establishes baseline operating characteristics during the fabrication process by measuring resistance values and determining voltage levels and timing characteristics before devices are deployed. This preliminary characterization enables consistent memory operation by building compensation structures into the devices during manufacturing, improving reliability without requiring complex external testing and adjustment systems.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where measured baseline characteristics are used to continuously adjust operational parameters during memory device operation. The system monitors performance deviations from established baselines and applies corrective adjustments to maintain consistent operation, achieving high reliability through a closed-loop control system that is integrated into the device architecture rather than requiring external complexity.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables more precise determination of operational parameters, enhancing the reliability and efficiency of memory operations by accounting for variations in memory device fabrication, leading to improved performance and consistency across memory arrays.

Implementation Method 1

A method is introduced to measure the resistive characteristics of access lines by forming current paths through them, allowing for the determination of resistance values

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS12183396B2Memory array structures and methods of forming memory array structures
Publication Date: 2024.12.31 MICRON TECHNOLOGY INC
  • US12183396B2 patent drawing
  • US12183396B2 patent drawing
  • US12183396B2 patent drawing

AI summary

Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.