Memory Array Address Mapping for Fewer Uncorrectable Errors
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Solution Overview
Problem
Semiconductor memory technologies face challenges in reducing uncorrectable memory errors due to systemic errors that overwhelm error correction codewords, particularly when physical locations of memory cells are mapped to common codewords, leading to uncorrectable errors.
Innovation Solution
The solution involves transforming addresses to distribute the physical locations of bits within memory arrays across multiple memory devices and arrays, using a control register to map memory arrays with higher error rates across multiple codewords, and employing arithmetic operations or reordering of address lines to create unique array addresses, thereby reducing the impact of systemic errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If physical locations of memory cells are mapped to common codewords, then memory access efficiency is improved, but uncorrectable errors increase due to systemic errors overwhelming error correction codewords
Solution Approach 1:
The patent segments the mapping relationship between physical memory locations and codewords by introducing intermediate logical addresses. Instead of direct mapping, multiple physical locations are grouped into logical address spaces, and error correction is performed at the logical address level. This segmentation prevents systemic errors from overwhelming individual codewords while maintaining efficient access through the logical addressing layer.
Solution Approach 2:
The patent introduces logical addresses as an intermediary between physical memory locations and error correction codewords. The logical address translation layer acts as a mediator that distributes physical location mappings across multiple codewords, preventing concentration of systemic errors in single codewords while maintaining access efficiency through the translation mechanism.
2Reliability
If error correction codewords are used to protect data, then data reliability is improved, but device complexity increases due to additional parity bits and correction circuitry
Solution Approach 1:
The patent makes the logical address translation mechanism multi-functional by having it simultaneously perform address mapping and error correction coordination. The same translation logic that maps physical addresses to logical addresses also manages the distribution of error correction information, eliminating the need for separate complex correction circuitry and reducing overall device complexity.
Solution Approach 2:
The logical address translation system performs self-service by automatically managing error correction without requiring external control logic. The translation mechanism inherently distributes error correction responsibilities across multiple codewords based on the mapping relationships, making the error correction process self-organizing and reducing the complexity of dedicated correction circuitry.
3Reliability
If redundant memory cells are used for error correction, then uncorrectable errors are reduced, but memory density decreases due to overhead from redundant cells
Solution Approach 1:
The patent merges the functions of data storage and error correction information by using the same physical memory cells to store both data bits and parity bits through logical address mapping. Instead of physically separate redundant cells, the system combines storage resources and uses logical addressing to organize error correction information, thereby improving reliability without sacrificing memory density.
Solution Approach 2:
The patent changes the organizational parameter of memory from physical redundancy to logical redundancy. By transforming the addressing scheme and mapping relationships rather than adding physical redundant cells, the system achieves error correction capability while maintaining the original physical memory density. The parameter change occurs at the logical address level rather than the physical cell level.
Data Source
AI summary
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.