Memory Array Address Mapping for Fewer Uncorrectable Errors
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Solution Overview
Problem
Semiconductor memory technologies face challenges in reducing uncorrectable memory errors due to systemic errors caused by physical locations within memory arrays, which can overload error correction codewords, leading to uncorrectable errors.
Innovation Solution
The solution involves transforming addresses to distribute bits of a codeword across multiple memory arrays, using a control register to map physical addresses to sets of memory arrays based on error rates, and employing arithmetic operations or reordering of address lines to create unique array addresses, thereby reducing the impact of systemic errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codewords are used to protect memory data, then reliability is improved, but systematic errors from physical locations can overload the error correction capability
Solution Approach 1:
The patent segments the codeword bits across multiple memory arrays by transforming addresses. Instead of storing all bits of a codeword in a single memory array, the address transformation distributes different bits of the same codeword across different memory arrays, thereby segmenting the storage location of codeword bits to avoid concentration of systematic errors.
Solution Approach 2:
The patent introduces a new dimension in address mapping by transforming logical addresses to physical addresses across multiple arrays. This dimensional transformation allows the system to map codeword bits to different physical locations in a multi-array space, adding spatial distribution capability that prevents systematic errors from affecting entire codewords.
2Productivity
If memory arrays are densely packed in cross-point arrays, then productivity is improved, but systematic errors at specific physical locations increase
Solution Approach 1:
The patent segments the dense cross-point memory arrays into multiple logical arrays and transforms addresses to distribute codeword bits across these segmented arrays. This segmentation maintains the physical density benefits while preventing systematic errors from affecting concentrated regions.
Solution Approach 2:
The patent applies local quality by treating different memory arrays differently through address transformation. Arrays that may be prone to systematic errors have their address mappings adjusted to distribute bits away from problematic regions, while maintaining optimal utilization of reliable regions.
Data Source
AI summary
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.