3D Memory Array Air-Gap Isolation for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in reducing parasitic capacitance between bit lines and source lines, which limits the frequency operation and efficiency of memory devices.
Innovation Solution
A 3D memory array is designed with vertically stacked memory cells, incorporating air gaps between bit lines and source lines to reduce capacitance, formed by trenching and sealing with insulating material, and using a ferroelectric memory film for efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If air gaps are introduced between bit lines and source lines to reduce parasitic capacitance, then frequency operation and device performance are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the isolation structure into multiple segments: shallow trenches filled with first dielectric material, deeper trenches filled with second dielectric material, and air gaps positioned between bit lines and source lines. This segmented approach reduces parasitic capacitance while managing the complexity through systematic structuring of the isolation regions.
Solution Approach 2:
The patent introduces air gaps as a three-dimensional feature between bit lines and source lines, moving beyond traditional planar isolation. By creating vertical air gaps and multi-level trench structures, the patent reduces parasitic capacitance in the vertical dimension while maintaining horizontal circuit functionality.
2Speed
If air gaps are introduced between bit lines and source lines to reduce parasitic capacitance, then frequency operation and device performance are improved, but manufacturing precision requirements increase
Solution Approach 1:
The isolation structure is divided into multiple manufacturable segments: shallow trenches filled with first dielectric material, deeper trenches filled with second dielectric material, and air gaps. This segmentation allows each component to be fabricated with standard precision requirements rather than requiring the entire complex structure to be manufactured in one step.
Solution Approach 2:
The patent performs preliminary trench formation and dielectric material deposition before creating the air gaps. By preparing the trench structures and filling them with dielectric materials in advance, the manufacturing process establishes a foundation that simplifies subsequent air gap formation and reduces the precision requirements for the final assembly.
3Area of stationary object
If vertically stacked memory cells are used to increase storage density, then area efficiency is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertically stacked memory cells. By stacking memory cells vertically, the patent increases storage density and area efficiency while utilizing the vertical dimension to accommodate additional circuit layers, word lines, and isolation structures.
Solution Approach 2:
The vertically stacked memory cell structure is divided into multiple functional segments: memory cells, transistors, bit lines, source lines, and isolation regions. Each segment is optimized for its specific function, allowing the complex three-dimensional structure to be manufactured through systematic, step-by-step fabrication processes.
4Object-generated harmful factors
If air gaps are used as isolation regions, then parasitic capacitance is reduced, but manufacturing precision and process complexity increase
Solution Approach 1:
The isolation system is segmented into multiple components: shallow trenches with first dielectric material, deeper trenches with second dielectric material, and air gaps. This segmentation allows each component to be manufactured with standard precision, and the combination of components achieves the overall goal of reducing parasitic capacitance without requiring ultra-high precision in any single step.
Solution Approach 2:
The patent uses dielectric materials as intermediary substances that fill the trenches and provide structural support. These dielectric intermediaries enable the formation of air gaps with controlled dimensions and positions, reducing the direct precision requirements for air gap formation while still achieving the desired parasitic capacitance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher-frequency operation and improved device performance by minimizing parasitic capacitance and enhancing data storage efficiency.
Implementation Method 1
By separating the bit lines and source lines with air gaps, capacitance between the bit lines and source lines can be reduced
Implementation Method 2
One type of non-volatile semiconductor memory is Ferroelectric random access memory (FeRAM, or FRAM)
Data Source
AI summary
A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.