Memory Array Annealing for Parallel Ising State Updates
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Solution Overview
Problem
High-dimensional Ising models with many spin states require significant computing resources and time for anneal computation, and hardware defects lead to computational errors during parallel processing.
Innovation Solution
A memory device with multiple arrays and circuits that selectively calculate local energy values from different rows or columns, allowing for parallel updates and reducing the impact of defective units by stochastic selection of memory units across arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the dimension of the Ising model is increased to handle more spin states, then the computational capability is improved, but the computing time and resource requirements increase significantly
Solution Approach 1:
The patent divides the Ising model computation into multiple independent blocks, each processing a subset of spin states. Multiple memory arrays (first memory array, second memory array, etc.) are used to simultaneously compute local energy values for different blocks, enabling parallel processing that reduces overall computing time while maintaining the ability to handle high-dimensional models
2Productivity
If parallel computation is used to speed up anneal computation, then the computing speed is improved, but the impact of hardware defects increases
Solution Approach 1:
The patent computes local energy values for different blocks independently using separate memory arrays and processing circuits. Each block's computation can be performed with different levels of precision or using different computational approaches based on local requirements, allowing the system to maintain high computing speed while managing defect impact locally rather than globally
Solution Approach 2:
The patent performs multiple computations of local energy values for the same spin state using different blocks and memory arrays. By having redundant computational paths established beforehand, the system can detect and correct errors from defective hardware components, ensuring computational accuracy is maintained despite parallel processing and hardware defects
Data Source
AI summary
A memory device, for executing an anneal computation with first state and a second state. The memory device includes a first memory array, a second memory array, a control circuit, a sensing circuit and a processing circuit. the control circuit selects a first horizontal row of memory units from the first memory array, and selects a second horizontal row of memory units from the second memory array. The sensing circuit computes a local energy value of the first state according to the current generated by the memory units of the first horizontal row, and computes a local energy value of the second state according to the current generated by the memory units of the second horizontal row. The processing circuit updates the first state and/or the second state according to the local energy value of the first state and the local energy value of the second state.